From patchwork Thu Nov 6 15:51:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 407617 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 17A4D1400A6 for ; Fri, 7 Nov 2014 03:01:41 +1100 (AEDT) Received: from localhost ([::1]:54644 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPVD-0001Et-Ah for incoming@patchwork.ozlabs.org; Thu, 06 Nov 2014 11:01:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36806) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLr-00024c-VM for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:52:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XmPLm-0004Kf-4G for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:59 -0500 Received: from mail-pa0-f49.google.com ([209.85.220.49]:60842) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLl-0004Ka-T3 for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:54 -0500 Received: by mail-pa0-f49.google.com with SMTP id lj1so1471824pab.36 for ; Thu, 06 Nov 2014 07:51:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bz5B3Oj7sIm/vkKHxhgiMYDuqBbZcAwYUvKfyr3QCNk=; b=WItiRKk6alNRqoecfOATZJ9AcDOuqE28RWVUoR9wfHBJeE4rcs0RScIDDJ48omiop7 0AHIEChRmcc98OrRW/ViAt67OiGunn+iMBkQtMuSC9uJv885ybbBUSlbZqVlheSJ/hdi xzqwt9UlSEJeXy0a5krDFTxAxssly7LLmKyeQQbPJqjhyZL3QCaov7vxnko4MKeR6kFc OiAb58Ym7c9a5Mv8efCyHC2rwz2p/8pGsuLB/dfDYX8pfXm9FFXLdxnwl4ZjCOljpl3e 7Eb3hsPB9RxkaoXgMuACaax8aUcxeBroqlnIXfjxcQM0C/yAaS91Rgbxy2JBA7AsyVyw 0Mhw== X-Gm-Message-State: ALoCoQkvl9Rdipi9hd+YgTF/i5Ug24BGdKrpk7RDcN+9Sx4dsVKiRQPqbeOCCvY0FjZ1AYgo34LK X-Received: by 10.68.106.66 with SMTP id gs2mr5279108pbb.76.1415289113397; Thu, 06 Nov 2014 07:51:53 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id z9sm6245585pdp.73.2014.11.06.07.51.51 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Nov 2014 07:51:52 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Thu, 6 Nov 2014 09:51:01 -0600 Message-Id: <1415289073-14681-15-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> References: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.49 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v10 14/26] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Add checks of SCR AW/FW bits when performing writes of CPSR. These SCR bits are used to control whether the CPSR masking bits can be adjusted from non-secure state. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- v8 -> v9 - Move cpsr_write mask filtering above mode switch. - Replace conditional checks removed in v8. v7 -> v8 - Fixed incorrect use of env->uncached_cpsr A/I/F to use env->daif instead. - Removed incorrect statement about SPSR to CPSR copies being affected by SCR.AW/FW. - Fix typo in comment. - Simpified cpsr_write logic v3 -> v4 - Fixed up conditions for ignoring CPSR.A/F updates by isolating to v7 and checking for the existence of EL3 and non-existence of EL2. --- target-arm/helper.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 948192b..9186fc7 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3644,6 +3644,8 @@ uint32_t cpsr_read(CPUARMState *env) void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) { + uint32_t changed_daif; + if (mask & CPSR_NZCV) { env->ZF = (~val) & CPSR_Z; env->NF = val; @@ -3666,8 +3668,57 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) env->GE = (val >> 16) & 0xf; } - env->daif &= ~(CPSR_AIF & mask); - env->daif |= val & CPSR_AIF & mask; + /* In a V7 implementation that includes the security extensions but does + * not include Virtualization Extensions the SCR.FW and SCR.AW bits control + * whether non-secure software is allowed to change the CPSR_F and CPSR_A + * bits respectively. + * + * In a V8 implementation, it is permitted for privileged software to + * change the CPSR A/F bits regardless of the SCR.AW/FW bits. + */ + if (!arm_feature(env, ARM_FEATURE_V8) && + arm_feature(env, ARM_FEATURE_EL3) && + !arm_feature(env, ARM_FEATURE_EL2) && + !arm_is_secure(env)) { + + changed_daif = (env->daif ^ val) & mask; + + if (changed_daif & CPSR_A) { + /* Check to see if we are allowed to change the masking of async + * abort exceptions from a non-secure state. + */ + if (!(env->cp15.scr_el3 & SCR_AW)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to switch CPSR_A flag from " + "non-secure world with SCR.AW bit clear\n"); + mask &= ~CPSR_A; + } + } + + if (changed_daif & CPSR_F) { + /* Check to see if we are allowed to change the masking of FIQ + * exceptions from a non-secure state. + */ + if (!(env->cp15.scr_el3 & SCR_FW)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to switch CPSR_F flag from " + "non-secure world with SCR.FW bit clear\n"); + mask &= ~CPSR_F; + } + + /* Check whether non-maskable FIQ (NMFI) support is enabled. + * If this bit is set software is not allowed to mask + * FIQs, but is allowed to set CPSR_F to 0. + */ + if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && + (val & CPSR_F)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to enable CPSR_F flag " + "(non-maskable FIQ [NMFI] support enabled)\n"); + mask &= ~CPSR_F; + } + } + } if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { if (bad_mode_switch(env, val & CPSR_M)) { @@ -3680,6 +3731,10 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) switch_mode(env, val & CPSR_M); } } + + env->daif &= ~(CPSR_AIF & mask); + env->daif |= val & CPSR_AIF & mask; + mask &= ~CACHED_CPSR_BITS; env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); }