From patchwork Thu Nov 6 15:50:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 407610 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 77DD61400A6 for ; Fri, 7 Nov 2014 02:58:51 +1100 (AEDT) Received: from localhost ([::1]:54619 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPST-0005JX-N9 for incoming@patchwork.ozlabs.org; Thu, 06 Nov 2014 10:58:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36747) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLm-0001vF-LM for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XmPLh-0004JK-Qt for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:54 -0500 Received: from mail-pa0-f48.google.com ([209.85.220.48]:44765) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLh-0004J6-KJ for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:49 -0500 Received: by mail-pa0-f48.google.com with SMTP id ey11so1472425pad.35 for ; Thu, 06 Nov 2014 07:51:49 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7sc7XMF6NGndZzUk+F3tr/PgcvK8+9y2prjIIHECphk=; b=Z3CdLQ7naJ8xXx/tGJ5ZvdoIVmMi/x6EqCjdq7k0VKUWYI6o16oJE1QxOTz+oU/cHD 3REr7yQLhWho19QGD7pvOkwtXtTaeZ48DbnB7DmHihwBOphf92BEtt6vlSPCKoNxh50H mrwYSJYI18WFFQBdhUysiroEAp+g2MfMpSyb8XLuXQ4fSDFleWYN7qUJZBQDgYgvY4hS sWNCsUPBAyGOjf7pfds8bE5rFZjjwJfHakWVpnzeB0bFO8p1RpP5eBjVlNdqS+6peCLX aBJed30MGRitGYp9lAE5GnUCEO0STpobgTnkSKDpaFeT0axLEveHp8Zcjf7nToWgBELD P6fg== X-Gm-Message-State: ALoCoQlVasWBStV92KTJS7chKTKw5NRF0dh7Nqip4EM6IvJa5hfYUqBmcMSU6xHahGFOQXnqqeRj X-Received: by 10.70.136.164 with SMTP id qb4mr5428958pdb.36.1415289109035; Thu, 06 Nov 2014 07:51:49 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id z9sm6245585pdp.73.2014.11.06.07.51.47 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Nov 2014 07:51:48 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Thu, 6 Nov 2014 09:50:59 -0600 Message-Id: <1415289073-14681-13-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> References: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.48 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v10 12/26] target-arm: add MVBAR support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Use MVBAR register as exception vector base address for exceptions taken to CPU monitor mode. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Fixed declaration order of the MVBARR register components v7 -> v8 - Changed the mvbar cp15 storage from uint64_t to uint32_t --- target-arm/cpu.h | 1 + target-arm/helper.c | 15 +++++++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7a860e6..cdc6f6d 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -211,6 +211,7 @@ typedef struct CPUARMState { uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; uint64_t vbar_el[4]; /* vector base address register */ + uint32_t mvbar; /* (monitor) vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint64_t contextidr_el1; /* Context ID. */ uint64_t tpidr_el0; /* User RW Thread register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index cb15ad4..a12ba1f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2356,6 +2356,9 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, .access = PL3_W | PL1_R, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, + { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, + .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, REGINFO_SENTINEL }; @@ -4272,16 +4275,16 @@ void arm_cpu_do_interrupt(CPUState *cs) cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ } - /* High vectors. */ - if (env->cp15.c1_sys & SCTLR_V) { - /* when enabled, base address cannot be remapped. */ + + if (new_mode == ARM_CPU_MODE_MON) { + addr += env->cp15.mvbar; + } else if (env->cp15.c1_sys & SCTLR_V) { + /* High vectors. When enabled, base address cannot be remapped. */ addr += 0xffff0000; } else { /* ARM v7 architectures provide a vector base address register to remap * the interrupt vector table. - * This register is only followed in non-monitor mode, and has a secure - * and un-secure copy. Since the cpu is always in a un-secure operation - * and is never in monitor mode this feature is always active. + * This register is only followed in non-monitor mode, and is banked. * Note: only bits 31:5 are valid. */ addr += env->cp15.vbar_el[1];