From patchwork Wed Nov 5 23:22:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 407192 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8A442140098 for ; Thu, 6 Nov 2014 10:26:29 +1100 (AEDT) Received: from localhost ([::1]:48969 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9y7-0000M2-F1 for incoming@patchwork.ozlabs.org; Wed, 05 Nov 2014 18:26:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56306) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vO-00045K-Pt for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xm9vJ-0004cR-OY for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:38 -0500 Received: from mail-pa0-f46.google.com ([209.85.220.46]:58077) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vJ-0004cH-Jm for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:33 -0500 Received: by mail-pa0-f46.google.com with SMTP id lf10so1746166pab.5 for ; Wed, 05 Nov 2014 15:23:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CzqlJT22eflyjSYIw+YYmgGeebcwsq8Y2t8MNPZuaYI=; b=AzzkhOO+qDay9B686wiDI7HJFPKllJqNvTpT6RNylZLOWaGbG0+CyFT9I4FHgER2dG eNA/xuu3MVdwqDTbwwhZ4VNKopKziQ4K/Ho0VkUAq0sST/+ciBI6Uyqt4KhJorL9mn3J alq7RvjGOgz5MDdsv3GGc/LguDiA5viLNI8LtEG/JHRiqmg4R9IzdO0HUoHml+U4176C HGrgypxqHFHmr3H9VuXtPf7lGqgv+dcYEsV+TCZxWWHbMvz8u2Tx5vxLUFSbDwUsGmM9 LuXeQ2gMXAMADC+9nkgbwYODk/ppyTkYAP7kQ4JNddk7jN/eaH6Sq+xhOoTRvoxoIhnU X7DQ== X-Gm-Message-State: ALoCoQmmgVfbzbi+kcM9zyz2+nk+q/eQ0L0sg8q+1HTtU+Xk/G91pubsZp2Rio1aqKVBgB0JJYjW X-Received: by 10.68.132.225 with SMTP id ox1mr320508pbb.85.1415229812998; Wed, 05 Nov 2014 15:23:32 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id r4sm4086349pdm.93.2014.11.05.15.23.31 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:23:32 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Wed, 5 Nov 2014 17:22:55 -0600 Message-Id: <1415229793-3278-9-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> References: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.46 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v9 08/26] target-arm: move AArch32 SCR into security reglist X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Define a new ARM CP register info list for the ARMv7 Security Extension feature. Register that list only for ARM cores with Security Extension/EL3 support. Moving AArch32 SCR into Security Extension register group. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v7 -> v8 - Fix SCR register fieldoffset to be offsetoflow32. - Rename v7_el3_cp_reginfo to el3_cp_reginfo and remove v7 feature check when defining. This allows all common v7/8 secure CP regs to be registered together leaving the v8_el3_cp_reginfo to only v8 specific EL3 registers. - Move SCR_EL3 into el3_cp_reginfo. v4 -> v5 - Added reset value on SCR_EL3 - Squashed SCR Migration fix (previously patch 33) This patch adds code to mark duplicate CP register registrations as NO_MIGRATE to avoid duplicate migrations. v3 -> v4 - Renamed security_cp_reginfo to v7_el3_cp_reginfo - Conditionalized define on whether v7 or v8 were enabled --- target-arm/helper.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 0471e6c..1be185d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -898,9 +898,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), .resetvalue = 0 }, - { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), - .resetvalue = 0, .writefn = scr_write }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, @@ -2335,11 +2332,18 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .access = PL3_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), .resetvalue = 0 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo el3_cp_reginfo[] = { { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, - .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), - .writefn = scr_write }, + .resetvalue = 0, .writefn = scr_write }, + { .name = "SCR", .type = ARM_CP_NO_MIGRATE, + .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), + .resetfn = arm_cp_reset_ignore, .writefn = scr_write }, REGINFO_SENTINEL }; @@ -2960,7 +2964,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } if (arm_feature(env, ARM_FEATURE_EL3)) { - define_arm_cp_regs(cpu, v8_el3_cp_reginfo); + if (arm_feature(env, ARM_FEATURE_V8)) { + define_arm_cp_regs(cpu, v8_el3_cp_reginfo); + } + define_arm_cp_regs(cpu, el3_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new