From patchwork Wed Nov 5 23:22:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 407189 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1531A140098 for ; Thu, 6 Nov 2014 10:24:21 +1100 (AEDT) Received: from localhost ([::1]:48951 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9w3-0005H4-3S for incoming@patchwork.ozlabs.org; Wed, 05 Nov 2014 18:24:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56253) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vJ-00041a-AR for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xm9vC-0004aY-9a for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:33 -0500 Received: from mail-pa0-f53.google.com ([209.85.220.53]:51857) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vC-0004aR-3Y for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:26 -0500 Received: by mail-pa0-f53.google.com with SMTP id kx10so1728404pab.26 for ; Wed, 05 Nov 2014 15:23:25 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vl6V5Cg0r3BVO18Ez8WteUC+HhAkPDvlZPwysxACnkQ=; b=TAx1tiwLGudEdFad4ru4BO06AQsHhmwgKhGvMF8BH6Au/beQrovQpBdTEZr51oIxxn kz7gCARbAVUxQHp9Pvr6P+Drjte0ubJGmj+sMKSTHnAaPXw8K5Lg4ig5phh0Yznl6xLu jcXjY4Yxbn4QGS0z8rWnUEMKSj7Mk/kktlpoBFHuiQbj9f4fLGaVsMpuYhvgsIGM5k4v 5Dl8GcR9WEAbwEzsBHxhB0cyeamuXBG1P+wYcsLhoBFk3MuDL9nwjmU5RiVy/aChzIJn Rm7Z+HYSoS2jXhhkkZFbyNEpAA0ZcaMPuIfIKBh0Gj8i0yeh/9+HvzN3mzMKUOjDQ7pF l8Sw== X-Gm-Message-State: ALoCoQlef36gdh1qEy9CJ/7SjQ0/99rYYjxjrC06V3moZ9znInYO9lucsMUz5ydvWyLfGxau2QO4 X-Received: by 10.68.68.235 with SMTP id z11mr485405pbt.102.1415229805266; Wed, 05 Nov 2014 15:23:25 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id r4sm4086349pdm.93.2014.11.05.15.23.23 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:23:24 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Wed, 5 Nov 2014 17:22:50 -0600 Message-Id: <1415229793-3278-4-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> References: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.53 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v9 03/26] target-arm: add banked register accessors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler If EL3 is in AArch32 state certain cp registers are banked (secure and non-secure instance). When reading or writing to coprocessor registers the following macros can be used. - A32_BANKED macros are used for choosing the banked register based on provided input security argument. This macro is used to choose the bank during translation of MRC/MCR instructions that are dependent on something other than the current secure state. - A32_BANKED_CURRENT macros are used for choosing the banked register based on current secure state. This is NOT to be used for choosing the bank used during translation as it breaks monitor mode. If EL3 is operating in AArch64 state coprocessor registers are not banked anymore. The macros use the non-secure instance (_ns) in this case, which is architecturally mapped to the AArch64 EL register. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v7 -> v8 - Move use_secure_reg() function to the TBFLAG patch. v5 -> v6 - Converted macro USE_SECURE_REG() into inlince function use_secure_reg() - Globally replace Aarch# with AArch# v4 -> v5 - Cleaned-up macros to try and alleviate misuse. Made A32_BANKED macros take secure arg indicator rather than relying on USE_SECURE_REG. Incorporated the A32_BANKED macros into the A32_BANKED_CURRENT. CURRENT is now the only one that automatically chooses based on current secure state. --- target-arm/cpu.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 0ea8602..34fae40 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -817,6 +817,33 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return arm_feature(env, ARM_FEATURE_AARCH64); } +/* Macros for accessing a specified CP register bank */ +#define A32_BANKED_REG_GET(_env, _regname, _secure) \ + ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) + +#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ + do { \ + if (_secure) { \ + (_env)->cp15._regname##_s = (_val); \ + } else { \ + (_env)->cp15._regname##_ns = (_val); \ + } \ + } while (0) + +/* Macros for automatically accessing a specific CP register bank depending on + * the current secure state of the system. These macros are not intended for + * supporting instruction translation reads/writes as these are dependent + * solely on the SCR.NS bit and not the mode. + */ +#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ + A32_BANKED_REG_GET((_env), _regname, \ + ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env)))) + +#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ + A32_BANKED_REG_SET((_env), _regname, \ + ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))), \ + (_val)) + void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx);