From patchwork Wed Nov 5 23:22:56 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 407195 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C9596140098 for ; Thu, 6 Nov 2014 10:28:25 +1100 (AEDT) Received: from localhost ([::1]:48987 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9zz-0003vC-TN for incoming@patchwork.ozlabs.org; Wed, 05 Nov 2014 18:28:23 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56334) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vR-0004AB-0c for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xm9vL-0004cs-EL for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:40 -0500 Received: from mail-pd0-f169.google.com ([209.85.192.169]:63983) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vL-0004cl-99 for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:35 -0500 Received: by mail-pd0-f169.google.com with SMTP id y10so1679656pdj.28 for ; Wed, 05 Nov 2014 15:23:34 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WygOHmxA4KSTDDs/e2hrIbEfHUF4BZvWgeA3pD0lXNg=; b=SXW7gVNkrzmkjAEDIeVM2Q1jh3IS5E5AGNmvcPOWhgJmgZx6XszAlog9JkaFF25O2R W189IQE9wi75Yq/JsQlpmG3QlUFsHEqwScTgCV44Q2LoYzb2g1To2wV4zEb30fNdC448 /cYNVOwvAjP5KWcZ3xfbztP7gDmqARynZIEXC3q7Pov1lLmVbMjHWiujhfGBYDrZoUsI cNe1GRRjD6dmDNWT8uup0QKBDZab10koTNU/UTxIiyavQq8UJRvWQb7cXmofbOOL1FsC q8jueX1hXe0bGtTEF7C9flHU9cUGsfllvVwBKKQwnuVV9AHO72dVgNwac7CleMO7CR/+ +d6Q== X-Gm-Message-State: ALoCoQmf7ihGVdJhSwgVBdWo0ykPgt9rEAUV1AuaUDkTFcKx/qnhN+ka0XGQJENtDoPMl6XyXNyf X-Received: by 10.68.250.196 with SMTP id ze4mr621856pbc.2.1415229814756; Wed, 05 Nov 2014 15:23:34 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id r4sm4086349pdm.93.2014.11.05.15.23.33 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:23:33 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Wed, 5 Nov 2014 17:22:56 -0600 Message-Id: <1415229793-3278-10-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> References: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.169 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v9 09/26] target-arm: implement IRQ/FIQ routing to Monitor mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- target-arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 1be185d..3086c2c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4233,12 +4233,21 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Disable IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I; offset = 4; + if (env->cp15.scr_el3 & SCR_IRQ) { + /* IRQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + mask |= CPSR_F; + } break; case EXCP_FIQ: new_mode = ARM_CPU_MODE_FIQ; addr = 0x1c; /* Disable FIQ, IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I | CPSR_F; + if (env->cp15.scr_el3 & SCR_FIQ) { + /* FIQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + } offset = 4; break; case EXCP_SMC: