From patchwork Wed Nov 5 07:22:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tiejun Chen X-Patchwork-Id: 406890 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 73AEB140079 for ; Wed, 5 Nov 2014 18:28:29 +1100 (AEDT) Received: from localhost ([::1]:44798 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xlv11-0007Ob-Dd for incoming@patchwork.ozlabs.org; Wed, 05 Nov 2014 02:28:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56514) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xlv0f-000749-8X for qemu-devel@nongnu.org; Wed, 05 Nov 2014 02:28:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xlv0a-0006A9-1F for qemu-devel@nongnu.org; Wed, 05 Nov 2014 02:28:05 -0500 Received: from mga11.intel.com ([192.55.52.93]:52706) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xlv0Z-00069y-QR for qemu-devel@nongnu.org; Wed, 05 Nov 2014 02:27:59 -0500 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP; 04 Nov 2014 23:27:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,862,1389772800"; d="scan'208";a="411671840" Received: from tchen0-linux.bj.intel.com ([10.238.135.73]) by FMSMGA003.fm.intel.com with ESMTP; 04 Nov 2014 23:19:27 -0800 From: Tiejun Chen To: mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, aliguori@amazon.com Date: Wed, 5 Nov 2014 15:22:58 +0800 Message-Id: <1415172179-7965-1-git-send-email-tiejun.chen@intel.com> X-Mailer: git-send-email 1.9.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 Cc: xen-devel@lists.xensource.com, allen.m.kay@intel.com, qemu-devel@nongnu.org Subject: [Qemu-devel] [RFC][PATCH 1/2] hw:xen:xen_pt: register isa bridge specific to IGD passthrough X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We need this instance to passthrough some config fields of PCH. Signed-off-by: Tiejun Chen --- hw/xen/xen_pt.c | 112 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c index c1bf357..403c33f 100644 --- a/hw/xen/xen_pt.c +++ b/hw/xen/xen_pt.c @@ -60,6 +60,7 @@ #include "xen_pt.h" #include "qemu/range.h" #include "exec/address-spaces.h" +#include "qapi/visitor.h" #define XEN_PT_NR_IRQS (256) static uint8_t xen_pt_mapped_machine_irq[XEN_PT_NR_IRQS] = {0}; @@ -829,3 +830,114 @@ static void xen_pci_passthrough_register_types(void) } type_init(xen_pci_passthrough_register_types) + +typedef struct { + uint16_t gpu_device_id; + uint16_t pch_device_id; +} XenIGDDeviceIDInfo; + +/* In real world different GPU should have different PCH. But actually + * the different PCH DIDs likely map to different PCH SKUs. We do the + * same thing for the GPU. For PCH, the different SKUs are going to be + * all the same silicon design and implementation, just different + * features turn on and off with fuses. The SW interfaces should be + * consistent across all SKUs in a given family (eg LPT). But just same + * features may not be supported. + * + * Most of these different PCH features probably don't matter to the + * Gfx driver, but obviously any difference in display port connections + * will so it should be fine with any PCH in case of passthrough. + * + * So currently use one PCH version, 0x8c4e, to cover all HSW(Haswell) + * scenarios, 0x9cc3 for BDW(Broadwell). + */ +static const XenIGDDeviceIDInfo xen_igd_combo_id_infos[] = { + /* HSW Classic */ + {0x0402, 0x8c4e}, /* HSWGT1D, HSWD_w7 */ + {0x0406, 0x8c4e}, /* HSWGT1M, HSWM_w7 */ + {0x0412, 0x8c4e}, /* HSWGT2D, HSWD_w7 */ + {0x0416, 0x8c4e}, /* HSWGT2M, HSWM_w7 */ + {0x041E, 0x8c4e}, /* HSWGT15D, HSWD_w7 */ + /* HSW ULT */ + {0x0A06, 0x8c4e}, /* HSWGT1UT, HSWM_w7 */ + {0x0A16, 0x8c4e}, /* HSWGT2UT, HSWM_w7 */ + {0x0A26, 0x8c4e}, /* HSWGT3UT, HSWM_w7 */ + {0x0A2E, 0x8c4e}, /* HSWGT3UT28W, HSWM_w7 */ + {0x0A1E, 0x8c4e}, /* HSWGT2UX, HSWM_w7 */ + {0x0A0E, 0x8c4e}, /* HSWGT1ULX, HSWM_w7 */ + /* HSW CRW */ + {0x0D26, 0x8c4e}, /* HSWGT3CW, HSWM_w7 */ + {0x0D22, 0x8c4e}, /* HSWGT3CWDT, HSWD_w7 */ + /* HSW Server */ + {0x041A, 0x8c4e}, /* HSWSVGT2, HSWD_w7 */ + /* HSW SRVR */ + {0x040A, 0x8c4e}, /* HSWSVGT1, HSWD_w7 */ + /* BSW */ + {0x1606, 0x9cc3}, /* BDWULTGT1, BDWM_w7 */ + {0x1616, 0x9cc3}, /* BDWULTGT2, BDWM_w7 */ + {0x1626, 0x9cc3}, /* BDWULTGT3, BDWM_w7 */ + {0x160E, 0x9cc3}, /* BDWULXGT1, BDWM_w7 */ + {0x161E, 0x9cc3}, /* BDWULXGT2, BDWM_w7 */ + {0x1602, 0x9cc3}, /* BDWHALOGT1, BDWM_w7 */ + {0x1612, 0x9cc3}, /* BDWHALOGT2, BDWM_w7 */ + {0x1622, 0x9cc3}, /* BDWHALOGT3, BDWM_w7 */ + {0x162B, 0x9cc3}, /* BDWHALO28W, BDWM_w7 */ + {0x162A, 0x9cc3}, /* BDWGT3WRKS, BDWM_w7 */ + {0x162D, 0x9cc3}, /* BDWGT3SRVR, BDWM_w7 */ +}; + +static void xen_igd_passthrough_pciisabridge_get_pci_device_id(Object *obj, + Visitor *v, + void *opaque, + const char *name, + Error **errp) +{ + uint32_t gpu_id = 0xffff, pch_id = 0xffff; + XenHostPCIDevice hdev; + int r = 0, num; + + r = xen_host_pci_device_get(&hdev, 0, 0, 0x02, 0); + if (!r) { + gpu_id = hdev.device_id; + + num = ARRAY_SIZE(xen_igd_combo_id_infos); + for (r = 0; r < num; r++) + if (gpu_id == xen_igd_combo_id_infos[r].gpu_device_id) + pch_id = xen_igd_combo_id_infos[r].pch_device_id; + } + + visit_type_uint32(v, &pch_id, name, errp); +} + +static void xen_igd_passthrough_isa_bridge_initfn(Object *obj) +{ + object_property_add(obj, "device-id", "int", + xen_igd_passthrough_pciisabridge_get_pci_device_id, + NULL, NULL, NULL, NULL); +} + +static void xen_igd_passthrough_isa_bridge_class_init(ObjectClass *klass, + void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + dc->desc = "XEN IGD PASSTHROUGH ISA bridge"; + k->class_id = PCI_CLASS_BRIDGE_ISA; + k->vendor_id = PCI_VENDOR_ID_INTEL; +}; + +static TypeInfo xen_igd_passthrough_isa_bridge_info = { + .name = "xen-igd-passthrough-isa-bridge", + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(PCIDevice), + .instance_init = xen_igd_passthrough_isa_bridge_initfn, + .class_init = xen_igd_passthrough_isa_bridge_class_init, +}; + +static void xen_igd_passthrough_isa_bridge_register_types(void) +{ + type_register_static(&xen_igd_passthrough_isa_bridge_info); +} + +type_init(xen_igd_passthrough_isa_bridge_register_types);