From patchwork Thu Oct 30 22:12:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 405466 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 077EA140085 for ; Sat, 1 Nov 2014 05:12:52 +1100 (AEDT) Received: from localhost ([::1]:40551 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkGgr-0000kN-QF for incoming@patchwork.ozlabs.org; Fri, 31 Oct 2014 14:12:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36912) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE4y-00045e-1l for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:27:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxxW-00063z-UG for qemu-devel@nongnu.org; Thu, 30 Oct 2014 18:12:52 -0400 Received: from mail-pa0-f44.google.com ([209.85.220.44]:62683) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxxW-00063G-LE for qemu-devel@nongnu.org; Thu, 30 Oct 2014 18:12:46 -0400 Received: by mail-pa0-f44.google.com with SMTP id bj1so6400455pad.3 for ; Thu, 30 Oct 2014 15:12:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eE7MiMX60PS9RhnNBEqqQw6scYi4didgHoPMI2sha/8=; b=jBEBxtihN9bLmDh+bBAY8i6TtUNvMVHnYlDHyal9fpWbdD4exbq7DsAyFGtY2cArbY n1hRzpBjFkGz6bs5sh9sfQD00sSNzEo/2DGVnLQHcKOJQ7gt8YPH5e0P9OZaFR/giZAG GDx5M8RDYd7fumCQ4OtnHY1wRz8XmhNWn7EUxCv2vtdfFTsbocE2V4BFkowe0jRA3DW0 mOTBMwncFF/AynuLeRoeakPmo5UQECz9aCw2BSvX5Lvh5/GBCfBRfaZj6eDnlElyoF/p +T5Ou2bQOo4tuQ8BGm4eJ6SMPi8P7COB7/qxmakzSMVNl5uGvbr10OHdYwPBnT3tUjkm Hx4A== X-Gm-Message-State: ALoCoQli9cjoIRVynYtfGaVSdbkFMlgKrwMD8DV80SycGuPenty2eoxvJY1n6sM9bU2n5TFqp9/n X-Received: by 10.70.61.68 with SMTP id n4mr20655426pdr.60.1414707166047; Thu, 30 Oct 2014 15:12:46 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id h3sm7270163pdl.22.2014.10.30.15.12.44 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 15:12:45 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, christoffer.dall@linaro.org Date: Thu, 30 Oct 2014 17:12:02 -0500 Message-Id: <1414707132-24588-7-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1414707132-24588-1-git-send-email-greg.bellows@linaro.org> References: <1414707132-24588-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.44 Cc: daniel.thompson@linaro.org Subject: [Qemu-devel] [PATCH v2 06/16] hw/intc/arm_gic: Add Interrupt Group Registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Interrupt Group Registers (previously called Interrupt Security Registers) as defined in GICv1 with Security Extensions or GICv2 allow to configure interrupts as Secure (Group0) or Non-secure (Group1). In GICv2 these registers are implemented independent of the existence of Security Extensions. Signed-off-by: Fabian Aggeler --- v1 -> v2 - Add clarifying comments to gic_dist_readb/writeb on interrupt group register update - Swap GIC_SET_GROUP0/1 macro logic. Setting the irq_state.group field for group 0 should clear the bit not set it. Similarly, setting the field for group 1 should set the bit not clear it. --- hw/intc/arm_gic.c | 49 +++++++++++++++++++++++++++++++++++++--- hw/intc/arm_gic_common.c | 1 + hw/intc/gic_internal.h | 4 ++++ include/hw/intc/arm_gic_common.h | 1 + 4 files changed, 52 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index bee71a1..36ac188 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -312,8 +312,27 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset) if (offset < 0x08) return 0; if (offset >= 0x80) { - /* Interrupt Security , RAZ/WI */ - return 0; + /* Interrupt Group Registers + * + * For GIC with Security Extn and Non-secure access RAZ/WI + * For GICv1 without Security Extn RAZ/WI + */ + res = 0; + if (!(s->security_extn && ns_access()) && + ((s->revision == 1 && s->security_extn) + || s->revision == 2)) { + /* Every byte offset holds 8 group status bits */ + irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; + if (irq >= s->num_irq) { + goto bad_reg; + } + for (i = 0; i < 8; i++) { + if (!GIC_TEST_GROUP0(irq + i, cm)) { + res |= (1 << i); + } + } + } + return res; } goto bad_reg; } else if (offset < 0x200) { @@ -457,7 +476,31 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, } else if (offset < 4) { /* ignored. */ } else if (offset >= 0x80) { - /* Interrupt Security Registers, RAZ/WI */ + /* Interrupt Group Registers + * + * For GIC with Security Extn and Non-secure access RAZ/WI + * For GICv1 without Security Extn RAZ/WI + */ + if (!(s->security_extn && ns_access()) && + ((s->revision == 1 && s->security_extn) + || s->revision == 2)) { + /* Every byte offset holds 8 group status bits */ + irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; + if (irq >= s->num_irq) { + goto bad_reg; + } + for (i = 0; i < 8; i++) { + /* Group bits are banked for private interrupts (internal)*/ + int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; + if (value & (1 << i)) { + /* Group1 (Non-secure) */ + GIC_SET_GROUP1(irq + i, cm); + } else { + /* Group0 (Secure) */ + GIC_SET_GROUP0(irq + i, cm); + } + } + } } else { goto bad_reg; } diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index e35049d..28f3b2a 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -52,6 +52,7 @@ static const VMStateDescription vmstate_gic_irq_state = { VMSTATE_UINT8(level, gic_irq_state), VMSTATE_BOOL(model, gic_irq_state), VMSTATE_BOOL(edge_trigger, gic_irq_state), + VMSTATE_UINT8(group, gic_irq_state), VMSTATE_END_OF_LIST() } }; diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index e87ef36..f01955a 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -50,6 +50,10 @@ s->priority1[irq][cpu] : \ s->priority2[(irq) - GIC_INTERNAL]) #define GIC_TARGET(irq) s->irq_target[irq] +#define GIC_SET_GROUP0(irq, cm) (s->irq_state[irq].group &= ~(cm)) +#define GIC_SET_GROUP1(irq, cm) (s->irq_state[irq].group |= (cm)) +#define GIC_TEST_GROUP0(irq, cm) ((s->irq_state[irq].group & (cm)) == 0) + /* The special cases for the revision property: */ #define REV_11MPCORE 0 diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index 7825134..b78981e 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -42,6 +42,7 @@ typedef struct gic_irq_state { uint8_t level; bool model; /* 0 = N:N, 1 = 1:N */ bool edge_trigger; /* true: edge-triggered, false: level-triggered */ + uint8_t group; } gic_irq_state; typedef struct GICState {