From patchwork Thu Oct 30 22:12:00 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 405363 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D1D1514007F for ; Sat, 1 Nov 2014 03:01:28 +1100 (AEDT) Received: from localhost ([::1]:38580 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkEdj-0003Ib-1N for incoming@patchwork.ozlabs.org; Fri, 31 Oct 2014 12:01:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34664) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE4y-00010h-TF for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:26:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxxU-00060i-6t for qemu-devel@nongnu.org; Thu, 30 Oct 2014 18:12:52 -0400 Received: from mail-pd0-f178.google.com ([209.85.192.178]:63275) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxxU-000605-1D for qemu-devel@nongnu.org; Thu, 30 Oct 2014 18:12:44 -0400 Received: by mail-pd0-f178.google.com with SMTP id fp1so6023922pdb.9 for ; Thu, 30 Oct 2014 15:12:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EyhpEmts5otFJ3vaG+i4MjYdwqjbwJiN0zd8/nkqNFY=; b=GFQ3jnSiRJH76Pxd18pO7nId+re0NSwDAH5CC0ZwGpoAOGmLUXO34yQfG8hcWNsYYH dh1uL/qCmjn8QlKJdyt5AU/1fCTUtZdHdelz0anOeh9A2vzwTgxgCnRdTILPUeI6g2D0 u9Krs/2DKH5qBYPGO2iu5vPdEagEPmxMpGsWhAZhSePQq3RjwIpvYjAyzaGIy8dxIcKZ YYiHae5usvcETLci0lzeACq7vX0BIkWZ2cxuSrS4nhF7Er/QoperDd2P1rwe5MYcfJ4a 0mxvDLeq5qq303J0fpWjLn726NoBua8af2VohuRxqv8tE6jHA2FhwuxHmQHdS1ztyRhd mtyA== X-Gm-Message-State: ALoCoQm8/Q+pQwPB0NBF20P1GKdDxrCxD3p/XBqO4ZdHpowkf7r4UAYU0ni5ZIjhnpu/uMCqUq6J X-Received: by 10.70.51.195 with SMTP id m3mr20337519pdo.27.1414707163139; Thu, 30 Oct 2014 15:12:43 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id h3sm7270163pdl.22.2014.10.30.15.12.41 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 15:12:41 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, christoffer.dall@linaro.org Date: Thu, 30 Oct 2014 17:12:00 -0500 Message-Id: <1414707132-24588-5-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1414707132-24588-1-git-send-email-greg.bellows@linaro.org> References: <1414707132-24588-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.178 Cc: daniel.thompson@linaro.org Subject: [Qemu-devel] [PATCH v2 04/16] hw/intc/arm_gic: Add Security Extensions property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler The existing implementation does not support Security Extensions mentioned in the GICv1 and GICv2 architecture specification. Security Extensions are not available on all GICs. This property makes it possible to enable Security Extensions. It also makes GICD_TYPER/ICDICTR.SecurityExtn RAO for GICs which implement Security Extensions. Signed-off-by: Fabian Aggeler --- v1 -> v2 - Change GICState security extension property from a uint8 type to bool --- hw/intc/arm_gic.c | 5 ++++- hw/intc/arm_gic_common.c | 1 + include/hw/intc/arm_gic_common.h | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index ea05f8f..0ee7778 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -298,7 +298,10 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset) if (offset == 0) return s->enabled; if (offset == 4) - return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); + /* Interrupt Controller Type Register */ + return ((s->num_irq / 32) - 1) + | ((NUM_CPU(s) - 1) << 5) + | (s->security_extn << 10); if (offset < 0x08) return 0; if (offset >= 0x80) { diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 18b01ba..e35049d 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -149,6 +149,7 @@ static Property arm_gic_common_properties[] = { * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) */ DEFINE_PROP_UINT32("revision", GICState, revision, 1), + DEFINE_PROP_BOOL("security-extn", GICState, security_extn, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index 01c6f24..7825134 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -105,6 +105,7 @@ typedef struct GICState { MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ uint32_t num_irq; uint32_t revision; + bool security_extn; int dev_fd; /* kvm device fd if backed by kvm vgic support */ } GICState;