From patchwork Thu Oct 30 22:12:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 405424 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id AEA2914007F for ; Sat, 1 Nov 2014 04:19:26 +1100 (AEDT) Received: from localhost ([::1]:39758 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkFrA-0000EG-1C for incoming@patchwork.ozlabs.org; Fri, 31 Oct 2014 13:19:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59859) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE4w-0000Rt-48 for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:27:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xjxxg-0006Et-Fj for qemu-devel@nongnu.org; Thu, 30 Oct 2014 18:13:02 -0400 Received: from mail-pd0-f175.google.com ([209.85.192.175]:43169) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xjxxg-0006EM-AE for qemu-devel@nongnu.org; Thu, 30 Oct 2014 18:12:56 -0400 Received: by mail-pd0-f175.google.com with SMTP id y13so5980300pdi.20 for ; Thu, 30 Oct 2014 15:12:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mQZmt+cBWJ6wsmJV2K7cst8mDlvVt6pPOkTldggfXHU=; b=iWAyCFupsvDKhe4yxe5L6ivrpPEtsnXXOpFsU6Da7lz0q+Q4bVOiHf6zWKupMSymGV OvILCN5T1Fr5L9XJFUqm6KKtCpfTH5vOLoaIiDYPhAoSvduaYTwKR8bNex4m3h625BCw agVryw/XqkseSXYh9c+fvJKk6N5SyLMoVNcTt9NOZ+wbgCnNl2SOTp1+rLRGxv1ipb/d xeppWfnv3TfbtIlLLblSMcWS436oeo25LBCNRTaCKVtgx2Z9QF/W5VqvNGaWDAJpjLB7 0KT1aL4qURVz89Wqpvgck1b85vaoSjaKlItPqyaFAq8kVTK7/9ar4r2sIHw8AKygIqrm CDzg== X-Gm-Message-State: ALoCoQnETMRXby592/dblcyfjNi4js370c/u8x+r2BCpe4wjb/Gk4GyFTFHXt3c5QyIA5PqX0Z1f X-Received: by 10.68.168.100 with SMTP id zv4mr20517029pbb.132.1414707175694; Thu, 30 Oct 2014 15:12:55 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id h3sm7270163pdl.22.2014.10.30.15.12.54 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 15:12:55 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, christoffer.dall@linaro.org Date: Thu, 30 Oct 2014 17:12:08 -0500 Message-Id: <1414707132-24588-13-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1414707132-24588-1-git-send-email-greg.bellows@linaro.org> References: <1414707132-24588-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.175 Cc: daniel.thompson@linaro.org Subject: [Qemu-devel] [PATCH v2 12/16] hw/intc/arm_gic: Change behavior of EOIR writes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Grouping (GICv2) and Security Extensions change the behavior of EOIR writes. Completing Group0 interrupts is only allowed from Secure state and completing Group1 interrupts from Secure state is only allowed if AckCtl bit is set. Signed-off-by: Fabian Aggeler --- v1 -> v2 - Fix issue with EOIR writes involving AckCtl. AckCtl is ignored on EOIR group 1 interrupts when non-secure. Group 1 interrupts are only ignored when secure and AckCTl is clear. --- hw/intc/arm_gic.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 15fd660..2d83225 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -384,6 +384,21 @@ void gic_complete_irq(GICState *s, int cpu, int irq) GIC_SET_PENDING(irq, cm); update = 1; } + } else if ((s->revision >= 2 && !s->security_extn) + || (s->security_extn && !ns_access())) { + /* Handle GICv2 without Security Extensions or GIC with Security + * Extensions and a secure write. + */ + if (!GIC_TEST_GROUP0(irq, cm) && !ns_access() + && !(s->cpu_control[cpu][0] & GICC_CTLR_S_ACK_CTL)) { + /* Unpredictable. We choose to ignore. */ + DPRINTF("EOI for Group1 interrupt %d ignored " + "(AckCtl disabled)\n", irq); + return; + } + } else if (s->security_extn && ns_access() && GIC_TEST_GROUP0(irq, cm)) { + DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); + return; } if (irq != s->running_irq[cpu]) {