From patchwork Thu Oct 30 21:28:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 405382 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 69FEB14007F for ; Sat, 1 Nov 2014 03:25:00 +1100 (AEDT) Received: from localhost ([::1]:38910 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkF0U-00086M-AI for incoming@patchwork.ozlabs.org; Fri, 31 Oct 2014 12:24:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47722) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE67-0002C4-Mo for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:28:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxHT-0004jn-Bz for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:24 -0400 Received: from mail-pd0-f175.google.com ([209.85.192.175]:58384) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxHT-0004iy-3X for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:19 -0400 Received: by mail-pd0-f175.google.com with SMTP id y13so5921025pdi.20 for ; Thu, 30 Oct 2014 14:29:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9CV9KNZJyoiNcYUeDg2qNQwQ6OZJam9FGrkPZ2HHwP0=; b=RZsw6LtpOHwNy0g6iFJYTKCLF4dFfU/nWucJ4ce//EHjzOhTe02k/anI/vswalRb1P e7YjtR8NfNSHd699fgJYCT26ZKZZDIbhWX3au9ZgbKWN0sOMiR2zTLJzj4QcMFXRYx1k NWevAHUZnEUwxEOFCIPWN+57cyrMn0B8pJIQs6xVPEiAMmQ/bnj09+mkdXMJtnotqYZT E1RmXWCzNON/Tl/ADZfJtBFz/Y1Q3EIrrOZj4da/vNC/JnTQ3MVuqDKLVD58V4YmATxg QguxC/LUU9w9ZGALvI8ZDBI64xe1d6iUezmqv+Lov43+aQZTK1n9MHbdxXcroeRDixdO FobQ== X-Gm-Message-State: ALoCoQm+empCRG91cgZW+Crcxn1szd2+fQ12Nw2yUjOuahm+ThPd/T7wdcwSlmpqeN82u9NZDa6V X-Received: by 10.70.128.226 with SMTP id nr2mr20153399pdb.89.1414704558439; Thu, 30 Oct 2014 14:29:18 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id o5sm8017713pdr.50.2014.10.30.14.29.17 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 14:29:17 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Thu, 30 Oct 2014 16:28:38 -0500 Message-Id: <1414704538-17103-8-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> References: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.175 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v8 07/27] target-arm: insert AArch32 cpregs twice into hashtable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Prepare for cp register banking by inserting every cp register twice, once for secure world and once for non-secure world. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- v7 -> v8 - Updated define registers asserts to allow either a non-zero fieldoffset or non-zero bank_fieldoffsets. - Updated CP register hashing to always set the register fieldoffset when banked register offsets are specified. v5 -> v6 - Fixed NS-bit number in the CPREG hash lookup from 27 to 29. - Switched to dedicated CPREG secure flags. - Fixed disablement of reset and migration of common 32/64-bit registers. - Globally replace Aarch# with AArch# v4 -> v5 - Added use of ARM CP secure/non-secure bank flags during register processing in define_one_arm_cp_reg_with_opaque(). We now only register the specified bank if only one flag is specified, otherwise we register both a secure and non-secure instance. --- target-arm/helper.c | 98 ++++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 82 insertions(+), 16 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 959a46e..c1c6303 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3296,22 +3296,62 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, uint32_t *key = g_new(uint32_t, 1); ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; - if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) { - /* The AArch32 view of a shared register sees the lower 32 bits - * of a 64 bit backing field. It is not migratable as the AArch64 - * view handles that. AArch64 also handles reset. - * We assume it is a cp15 register if the .cp field is left unset. + + if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { + /* Register is banked (using both entries in array). + * Overwriting fieldoffset as the array is only used to define + * banked registers but later only fieldoffset is used. */ - if (r2->cp == 0) { - r2->cp = 15; + r2->fieldoffset = r->bank_fieldoffsets[nsbit]; + } + + if (state == ARM_CP_STATE_AA32) { + /* Clear the secure state flags and set based on incoming nsbit */ + r2->secure &= ~(ARM_CP_SECSTATE_S | ARM_CP_SECSTATE_NS); + r2->secure |= ARM_CP_SECSTATE_S << nsbit; + + if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { + /* If the register is banked and V8 is enabled then we don't need + * to migrate or reset the AArch32 version of the banked + * registers as this will be handled through the AArch64 view. + * If v7 then we don't need to migrate or reset the AArch32 + * non-secure bank as this will be handled through the AArch64 + * view. In this case the secure bank is not mirrored, so we must + * preserve it's reset criteria and allow it to be migrated. + * + * The exception to the above is cpregs with a crn of 13 + * (specifically FCSEIDR and CONTEXTIDR) in which case there may + * not be an AArch64 equivalent for one or either bank so migration + * and reset must be preserved. + */ + if (r->state == ARM_CP_STATE_BOTH) { + if ((arm_feature(&cpu->env, ARM_FEATURE_V8) && r->crn != 13) || + nsbit) { + r2->type |= ARM_CP_NO_MIGRATE; + r2->resetfn = arm_cp_reset_ignore; + } + } + } else if (!nsbit) { + /* The register is not banked so we only want to allow migration of + * the non-secure instance. + */ + r2->type |= ARM_CP_NO_MIGRATE; + r2->resetfn = arm_cp_reset_ignore; } - r2->type |= ARM_CP_NO_MIGRATE; - r2->resetfn = arm_cp_reset_ignore; + + if (r->state == ARM_CP_STATE_BOTH) { + /* We assume it is a cp15 register if the .cp field is left unset. + */ + if (r2->cp == 0) { + r2->cp = 15; + } + #ifdef HOST_WORDS_BIGENDIAN - if (r2->fieldoffset) { - r2->fieldoffset += sizeof(uint32_t); - } + if (r2->fieldoffset) { + r2->fieldoffset += sizeof(uint32_t); + } #endif + } } if (state == ARM_CP_STATE_AA64) { /* To allow abbreviation of ARMCPRegInfo @@ -3460,10 +3500,14 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, */ if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { if (r->access & PL3_R) { - assert(r->fieldoffset || r->readfn); + assert((r->fieldoffset || + (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || + r->readfn); } if (r->access & PL3_W) { - assert(r->fieldoffset || r->writefn); + assert((r->fieldoffset || + (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || + r->writefn); } } /* Bad type field probably means missing sentinel at end of reg list */ @@ -3476,8 +3520,30 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (r->state != state && r->state != ARM_CP_STATE_BOTH) { continue; } - add_cpreg_to_hashtable(cpu, r, opaque, state, - crm, opc1, opc2, SCR_NS); + if (state == ARM_CP_STATE_AA32) { + /* Under AArch32 CP registers can be common + * (same for secure and non-secure world) or banked. + */ + uint32_t s = + r->secure & (ARM_CP_SECSTATE_S | ARM_CP_SECSTATE_NS); + if (ARM_CP_SECSTATE_S == s) { + add_cpreg_to_hashtable(cpu, r, opaque, state, + crm, opc1, opc2, !SCR_NS); + } else if (ARM_CP_SECSTATE_NS == s) { + add_cpreg_to_hashtable(cpu, r, opaque, state, + crm, opc1, opc2, SCR_NS); + } else { + add_cpreg_to_hashtable(cpu, r, opaque, state, + crm, opc1, opc2, !SCR_NS); + add_cpreg_to_hashtable(cpu, r, opaque, state, + crm, opc1, opc2, SCR_NS); + } + } else { + /* AArch64 registers get mapped to non-secure instance + * of AArch32 */ + add_cpreg_to_hashtable(cpu, r, opaque, state, + crm, opc1, opc2, SCR_NS); + } } } }