From patchwork Thu Oct 30 21:28:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 405508 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E9E5514007D for ; Sat, 1 Nov 2014 06:02:06 +1100 (AEDT) Received: from localhost ([::1]:41332 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkHSW-0005HP-IB for incoming@patchwork.ozlabs.org; Fri, 31 Oct 2014 15:02:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52716) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE68-0001z8-AF for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:27:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxHQ-0004fw-Em for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:21 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:50515) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxHQ-0004eq-6X for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:16 -0400 Received: by mail-pa0-f51.google.com with SMTP id kq14so6287481pab.38 for ; Thu, 30 Oct 2014 14:29:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=shhnnCemJGlWrmUFBLy3rx5oHd7QlGVVhziwqozb34Y=; b=DM7F3U3ywXMeiFRPqUU9Q2JnalN5x53fwA1tAuE7/+L04QjD3xQSE215HtE53cfL09 kgMDf3bOYtGW5PS17HUPIZ2W/O158GJH7rR85tb2m1AaUeKQwAxwQQgBK5P5KHiFtpsJ RtMltQnfTezTQ3p9X/+zc4jarYjXHha6c7P+BAlmOaq3iwY8zPh3ap/D30o30vILeEvH 4pQPX6K60BEf0sDxenDM7FjDsvN7UkhtLzJFZmjbGaAI3ZEMBTqa/8IMb+R90YDcTH+L QN2LW/fFPkEB9SmlTX+8a6Fno2NLYIqXMie5n20Z/itGW2cON+JPIJ0e4wppWee+/YDR AIdA== X-Gm-Message-State: ALoCoQm8eBK9Bf7F6ztD60B4A9ExtUVs273kx24hyT7zweVEMFzDpnI8tupsPGa+iQqVq5XVx69R X-Received: by 10.70.11.2 with SMTP id m2mr20256385pdb.31.1414704555501; Thu, 30 Oct 2014 14:29:15 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id o5sm8017713pdr.50.2014.10.30.14.29.14 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 14:29:14 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Thu, 30 Oct 2014 16:28:36 -0500 Message-Id: <1414704538-17103-6-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> References: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.51 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v8 05/27] target-arm: add CPREG secure state support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- v7 -> v8 - Break up the fieldoffset union to avoid need for sometimes overwriting one bank when updating fieldoffset. This also removes the need for the #define short-cut introduced in v7. v6 -> v7 - Add naming for fieldoffset fields and macros for accessing. This was needed to overcome issues with the GCC-4.4 compiler. v5 -> v6 - Separate out secure CPREG flags - Add convenience macro for testing flags - Removed extraneous newline - Move add_cpreg_to_hashtable() functionality to a later commit for which it is dependent on. - Added comment explaining fieldoffset padding v4 -> v5 - Added ARM CP register secure and non-secure bank flags - Added setting of secure and non-secure flags furing registration --- target-arm/cpu.h | 41 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index ba621fa..51117fb 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -993,6 +993,24 @@ enum { ARM_CP_STATE_BOTH = 2, }; +/* ARM CP register secure state flags. These flags identify security state + * attributes for a given CP register entry. + * The existence of both or neither secure and non-secure flags indicates that + * the register has both a secure and non-secure hash entry. A single one of + * these flags causes the register to only be hashed for the specified + * security state. + * Although definitions may have any combination of the S/NS bits, each + * registered entry will only have one to identify whether the entry is secure + * or non-secure. + */ +enum { + ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ + ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ +}; + +/* Convenience macro for checking for a specific bit */ +#define ARM_CP_SECSTATE_TEST(_ri, _flag) (((_ri)->secure & (_flag)) == (_flag)) + /* Return true if cptype is a valid type field. This is used to try to * catch errors where the sentinel has been accidentally left off the end * of a list of registers. @@ -1127,6 +1145,8 @@ struct ARMCPRegInfo { int type; /* Access rights: PL*_[RW] */ int access; + /* Security state: ARM_CP_SECSTATE_* bits/values */ + int secure; /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when * this register was defined: can be used to hand data through to the * register read/write functions, since they are passed the ARMCPRegInfo*. @@ -1136,12 +1156,27 @@ struct ARMCPRegInfo { * fieldoffset is non-zero, the reset value of the register. */ uint64_t resetvalue; - /* Offset of the field in CPUARMState for this register. This is not - * needed if either: + /* Offset of the field in CPUARMState for this register. + * + * This is not needed if either: * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs * 2. both readfn and writefn are specified */ - ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ + ptrdiff_t fieldoffset; + + /* Offsets of the secure and non-secure fields in CPUARMState for the + * register if it is banked. These fields are only used during the static + * registration of a register. During hashing the bank associated + * with a given security state is copied to fieldoffset which is used from + * there on out. + * + * It is expected that register definitions use either fieldoffset or + * bank_fieldoffsets in the definition but not both. It is also expected + * that both bank offsets are set when defining a banked register. This + * use indicates that a register is banked. + */ + ptrdiff_t bank_fieldoffsets[2]; + /* Function for making any access checks for this register in addition to * those specified by the 'access' permissions bits. If NULL, no extra * checks required. The access check is performed at runtime, not at