From patchwork Thu Oct 30 21:28:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 405471 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id DFC6B140077 for ; Sat, 1 Nov 2014 05:22:41 +1100 (AEDT) Received: from localhost ([::1]:40705 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkGqN-00031i-Uv for incoming@patchwork.ozlabs.org; Fri, 31 Oct 2014 14:22:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42458) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE68-0003GE-Hq for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:27:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxHP-0004e1-8Z for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:20 -0400 Received: from mail-pa0-f54.google.com ([209.85.220.54]:34160) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxHP-0004d2-0M for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:15 -0400 Received: by mail-pa0-f54.google.com with SMTP id rd3so6310715pab.13 for ; Thu, 30 Oct 2014 14:29:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Xg74WMx5B1Y9Bbx3N7K5bNNv5kP+2a/QLWhpQnng/W4=; b=Em7B7JaTBB+MeFfBHkbqpLqRF9GZB/4jLPw+JS3NRCEhIY7MnHbtNb8+3mi5jnaV74 7HxSlrRXLfh66y65BnfHcQeBfPTcNx0AEYmLh5cgEaPoWl73Sd3ZlIxaTYiGRd4AZnO2 R6BGS8j96TPTAHjzDc03ojsRgq18dfrkVIZMgYAuPioa4dmMIoMvt1gHsgAUzCWC51EB 4yMGeM3jN+PpTdi9SutMHcKvoR6REzx0mxcskroQsgUcrckeIO4URHkTwTgjLcQH7HQm S6DV8btXPG2+bbEuZVwYVYxhvOGEUDZUSGVOrsEMnFCobnGknHI+6ssuScyioJWdeOoK 6vNg== X-Gm-Message-State: ALoCoQmzXyJQK+mcGNFjhwq5A12a48MY/fVTNEqa9uEuZP9oQF59VUKVTKyXvGfLZGAQ8M51M6/A X-Received: by 10.70.22.195 with SMTP id g3mr19917828pdf.37.1414704554105; Thu, 30 Oct 2014 14:29:14 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id o5sm8017713pdr.50.2014.10.30.14.29.12 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 14:29:13 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Thu, 30 Oct 2014 16:28:35 -0500 Message-Id: <1414704538-17103-5-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> References: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.54 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v8 04/27] target-arm: add non-secure Translation Block flag X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Sergey Fedorov This patch is based on idea found in patch at git://github.com/jowinter/qemu-trustzone.git f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by Johannes Winter . The TBFLAG captures the SCR NS secure state at the time when a TB is created so the correct bank is accessed on system register accesses. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v7 -> v8 - Moved and renamed use_secure_reg() to this patch. New name is access_secure_reg(). - Fixed function comment v5 -> v6 - Removed 64-bit NS TBFLAG macros as they are not needed - Added comment on DisasContext ns field - Replaced use of USE_SECURE_REG with use_secure_reg v4 -> v5 - Merge changes - Fixed issue where TB secure state flag was incorrectly being set based on secure state rather than NS setting. This caused an issue where monitor mode MRC/MCR accesses were always secure rather than being based on NS bit setting. - Added separate 64/32 TB secure state flags - Unconditionalized the setting of the DC ns bit - Removed IS_NS macro and replaced with direct usage. --- target-arm/cpu.h | 27 +++++++++++++++++++++++++++ target-arm/translate.c | 1 + target-arm/translate.h | 1 + 3 files changed, 29 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 5117d4d..ba621fa 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -817,6 +817,22 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return arm_feature(env, ARM_FEATURE_AARCH64); } +/* Function for determing whether guest cp register reads and writes should + * access the secure or non-secure bank of a cp register. When EL3 is + * operating in AArch32 state, the NS-bit determines whether the secure + * instance of a cp register should be used. When EL3 is AArch64 (or if + * it doesn't exist at all) then there is no register banking, and all + * accesses are to the non-secure version. + */ +static inline bool access_secure_reg(CPUARMState *env) +{ + bool ret = (arm_feature(env, ARM_FEATURE_EL3) && + !arm_el_is_aa64(env, 3) && + !(env->cp15.scr_el3 & SCR_NS)); + + return ret; +} + /* Macros for accessing a specified CP register bank */ #define A32_BANKED_REG_GET(_env, _regname, _secure) \ ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) @@ -1603,6 +1619,12 @@ static inline bool arm_singlestep_active(CPUARMState *env) */ #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) +/* Indicates whether cp register reads and writes by guest code should access + * the secure or nonsecure bank of banked registers; note that this is not + * the same thing as the current security state of the processor! + */ +#define ARM_TBFLAG_NS_SHIFT 22 +#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) /* Bit usage when in AArch64 state */ #define ARM_TBFLAG_AA64_EL_SHIFT 0 @@ -1647,6 +1669,8 @@ static inline bool arm_singlestep_active(CPUARMState *env) (((F) & ARM_TBFLAG_AA64_SS_ACTIVE_MASK) >> ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT) #define ARM_TBFLAG_AA64_PSTATE_SS(F) \ (((F) & ARM_TBFLAG_AA64_PSTATE_SS_MASK) >> ARM_TBFLAG_AA64_PSTATE_SS_SHIFT) +#define ARM_TBFLAG_NS(F) \ + (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, int *flags) @@ -1696,6 +1720,9 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (privmode) { *flags |= ARM_TBFLAG_PRIV_MASK; } + if (!(access_secure_reg(env))) { + *flags |= ARM_TBFLAG_NS_MASK; + } if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1)) { *flags |= ARM_TBFLAG_VFPEN_MASK; diff --git a/target-arm/translate.c b/target-arm/translate.c index 1d52e47..32eb7bb 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11005,6 +11005,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, #if !defined(CONFIG_USER_ONLY) dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0); #endif + dc->ns = ARM_TBFLAG_NS(tb->flags); dc->cpacr_fpen = ARM_TBFLAG_CPACR_FPEN(tb->flags); dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags); dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags); diff --git a/target-arm/translate.h b/target-arm/translate.h index 41a9071..f6ee789 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -20,6 +20,7 @@ typedef struct DisasContext { #if !defined(CONFIG_USER_ONLY) int user; #endif + bool ns; /* Use non-secure CPREG bank on access */ bool cpacr_fpen; /* FP enabled via CPACR.FPEN */ bool vfp_enabled; /* FP enabled via FPSCR.EN */ int vec_len;