From patchwork Thu Oct 30 21:28:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 405512 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 835C014007D for ; Sat, 1 Nov 2014 06:08:52 +1100 (AEDT) Received: from localhost ([::1]:41500 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkHZ4-0001rP-Hn for incoming@patchwork.ozlabs.org; Fri, 31 Oct 2014 15:08:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46790) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE69-0000tr-GM for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:27:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxHN-0004bV-Fg for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:20 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:43143) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxHN-0004an-9P for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:13 -0400 Received: by mail-pa0-f41.google.com with SMTP id rd3so6288014pab.28 for ; Thu, 30 Oct 2014 14:29:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W9Gk5UTdhL5oYmRYE2mukw6Big5TBCVY85hz1bZkACA=; b=Co4RczaGX79ZCIxWfu2j05GF7x7gOQRmKdJJcVkzH4QohKc+VKN03LZJg4oFsn/CWY 0zlrkef4/oJfu6x0lMv37ffKHHT2lqr1w+W4H+DrV1wU/j4auUMAcQCaji5cbQdnulF+ QulWGIOuLp45MMGp2g7WHpBoItKLDtRPmshfprYqyFo90NqthJyGdDlVPDx7n+WYS9pN sLadex5Neezq1WWuwdvab9jaVDYn4ymVPduqIANPip5QaMfIx1KcazArtBAX/HaHvyZV TfvALRrflDdxRwBJq0heUJWZ1+wN90PKTBvqGSeozwT6fsAIb/RnP0feSw99aUP6p9bo zkFw== X-Gm-Message-State: ALoCoQkF8s5xoJULtnEnZNeqAcn+YHXu90HM6o5dBNlgi2+RsRQHY5BnWeM8EaPO6Gfqj+v0i4XE X-Received: by 10.66.219.38 with SMTP id pl6mr20094927pac.43.1414704552510; Thu, 30 Oct 2014 14:29:12 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id o5sm8017713pdr.50.2014.10.30.14.29.11 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 14:29:11 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Thu, 30 Oct 2014 16:28:34 -0500 Message-Id: <1414704538-17103-4-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> References: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.41 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v8 03/27] target-arm: add banked register accessors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler If EL3 is in AArch32 state certain cp registers are banked (secure and non-secure instance). When reading or writing to coprocessor registers the following macros can be used. - A32_BANKED macros are used for choosing the banked register based on provided input security argument. This macro is used to choose the bank during translation of MRC/MCR instructions that are dependent on something other than the current secure state. - A32_BANKED_CURRENT macros are used for choosing the banked register based on current secure state. This is NOT to be used for choosing the bank used during translation as it breaks monitor mode. If EL3 is operating in AArch64 state coprocessor registers are not banked anymore. The macros use the non-secure instance (_ns) in this case, which is architecturally mapped to the AArch64 EL register. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v7 -> v8 - Move use_secure_reg() function to the TBFLAG patch. v5 -> v6 - Converted macro USE_SECURE_REG() into inlince function use_secure_reg() - Globally replace Aarch# with AArch# v4 -> v5 - Cleaned-up macros to try and alleviate misuse. Made A32_BANKED macros take secure arg indicator rather than relying on USE_SECURE_REG. Incorporated the A32_BANKED macros into the A32_BANKED_CURRENT. CURRENT is now the only one that automatically chooses based on current secure state. --- target-arm/cpu.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index be5d022..5117d4d 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -817,6 +817,33 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return arm_feature(env, ARM_FEATURE_AARCH64); } +/* Macros for accessing a specified CP register bank */ +#define A32_BANKED_REG_GET(_env, _regname, _secure) \ + ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) + +#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ + do { \ + if (_secure) { \ + (_env)->cp15._regname##_s = (_val); \ + } else { \ + (_env)->cp15._regname##_ns = (_val); \ + } \ + } while (0) + +/* Macros for automatically accessing a specific CP register bank depending on + * the current secure state of the system. These macros are not intended for + * supporting instruction translation reads/writes as these are dependent + * solely on the SCR.NS bit and not the mode. + */ +#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ + A32_BANKED_REG_GET((_env), _regname, \ + ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env)))) + +#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ + A32_BANKED_REG_SET((_env), _regname, \ + ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))), \ + (_val)) + void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx);