From patchwork Thu Oct 30 21:28:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 405364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A463614007D for ; Sat, 1 Nov 2014 03:01:40 +1100 (AEDT) Received: from localhost ([::1]:38583 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkEdu-0003eW-JK for incoming@patchwork.ozlabs.org; Fri, 31 Oct 2014 12:01:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57418) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE61-0004Vq-Kj for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:28:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxHv-0005Jn-Pz for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:54 -0400 Received: from mail-pa0-f52.google.com ([209.85.220.52]:49379) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxHv-0005Jh-KP for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:47 -0400 Received: by mail-pa0-f52.google.com with SMTP id fa1so6279979pad.11 for ; Thu, 30 Oct 2014 14:29:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wLgajuBAJEqQnGA52KffMrXtg9O2A72xOGJpJ11murA=; b=hiFcetsI2GpgDLsRJz0ARg6wER12WJ2iAXZdEPt6K999lHDp4hkgl30cvvJuh9FqP4 CNCsUfPq7rbl6N6HYEbTOj9tUUEjkZc77qdnshvVBtisdfaYMBpsSALJH3wlXnvU+bY6 xXRlGiNNxdoDZNrLT/tsfTT1S6bLp95wUVEdMkYPjzUoKJSCUs97VM4Ap/s03vkicvQd 1S/1EK4GQapXPtY3SyCdre4aErsYw9nvdAloNjB/MAXkAm8lcj0cP/Q5sJ1Gqu6IE61T aIt9UcBNyEDoLU/sDjcdLZ7fHtXfavO1naZf2yr58dKSGaFaq9+QBXOM7z9l891asrqp BzZA== X-Gm-Message-State: ALoCoQlZzFqUL0xZgVJR1ZJ8N7SgMT3281pLOXeRN4IY94xLR1MyWK+55JwJ5LO5MRzHfCOxzt46 X-Received: by 10.68.104.194 with SMTP id gg2mr9418799pbb.119.1414704587061; Thu, 30 Oct 2014 14:29:47 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id o5sm8017713pdr.50.2014.10.30.14.29.45 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 14:29:46 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Thu, 30 Oct 2014 16:28:57 -0500 Message-Id: <1414704538-17103-27-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> References: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.52 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v8 26/27] target-arm: make MAIR0/1 banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Added CP register info entries for the ARMv7 MAIR0/1 secure banks. Signed-off-by: Greg Bellows --- v5 -> v6 - Changed _el field variants to be array based --- target-arm/cpu.h | 12 +++++++++++- target-arm/helper.c | 8 +++++--- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 348ce73..1a76fc6 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -305,7 +305,17 @@ typedef struct CPUARMState { uint32_t c9_pmxevtyper; /* perf monitor event type */ uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ - uint64_t mair_el1; + union { /* Memory attribute redirection */ + struct { + uint64_t _unused_mair_0; + uint32_t mair0_ns; + uint32_t mair1_ns; + uint64_t _unused_mair_1; + uint32_t mair0_s; + uint32_t mair1_s; + }; + uint64_t mair_el[4]; + }; union { /* vector base address register */ struct { uint64_t _unused_vbar; diff --git a/target-arm/helper.c b/target-arm/helper.c index d782897..fd5f074 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -939,7 +939,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { */ { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1), + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), .resetvalue = 0 }, /* For non-long-descriptor page tables these are PRRR and NMRR; * regardless they still act as reads-as-written for QEMU. @@ -948,11 +948,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { */ { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, - .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), + offsetof(CPUARMState, cp15.mair0_ns) }, .resetfn = arm_cp_reset_ignore }, { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, - .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), + offsetof(CPUARMState, cp15.mair1_ns) }, .resetfn = arm_cp_reset_ignore }, { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,