From patchwork Thu Oct 30 21:28:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 405365 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 946E414007D for ; Sat, 1 Nov 2014 03:04:12 +1100 (AEDT) Received: from localhost ([::1]:38613 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkEgM-0007jN-EV for incoming@patchwork.ozlabs.org; Fri, 31 Oct 2014 12:04:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49715) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE66-0004VX-NF for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:28:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxHW-0004oS-Fv for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:27 -0400 Received: from mail-pd0-f179.google.com ([209.85.192.179]:65294) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxHW-0004nY-9x for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:22 -0400 Received: by mail-pd0-f179.google.com with SMTP id g10so5923493pdj.38 for ; Thu, 30 Oct 2014 14:29:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Jo6EbOWcTR9diUp+OJMgLSMyu5LWmFmR/PWmKrsdWm8=; b=BelZ5VyZB3Fyjxxte7F3UksdtD8s4GNF5rqlbkB6g5MkkijLEc+1IfX0aMXsUoltOn ihKI+pgbwGu/4OS3ptDWVDe42jEiWwK9iwBagLbzGp7PPVEpah6cZwW138GVcHUBbHN7 hsF277RXKrUOVckod8QDCM94ka0Ls5DkCcsKb05vBCVVDUJflWR1fWhFhU9E5Z/wnOia xY7t8ASwVqp06gy+hFJnzlXnf31BdaAieN8cPyzF6gRbl6Hslha92otfIxrNZtvs9EuP /m7M4Qoubk0+Z6veEBDMgVWzOsQ94iwuy6GzH6OjrbuvKc5ukjRfHitM1Pt+XR23KPj8 DBdw== X-Gm-Message-State: ALoCoQlklkLbAc0WFl1R61f7/Ukua10KEf8puA4SRc4bk1dvbhCTAcsO6Mn1SgthSDkhgLjNurkq X-Received: by 10.70.5.227 with SMTP id v3mr5031491pdv.165.1414704561609; Thu, 30 Oct 2014 14:29:21 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id o5sm8017713pdr.50.2014.10.30.14.29.19 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 14:29:20 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Thu, 30 Oct 2014 16:28:40 -0500 Message-Id: <1414704538-17103-10-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> References: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.179 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v8 09/27] target-arm: implement IRQ/FIQ routing to Monitor mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- target-arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 3fdd3c2..e73756d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4227,12 +4227,21 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Disable IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I; offset = 4; + if (env->cp15.scr_el3 & SCR_IRQ) { + /* IRQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + mask |= CPSR_F; + } break; case EXCP_FIQ: new_mode = ARM_CPU_MODE_FIQ; addr = 0x1c; /* Disable FIQ, IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I | CPSR_F; + if (env->cp15.scr_el3 & SCR_FIQ) { + /* FIQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + } offset = 4; break; case EXCP_SMC: