From patchwork Tue Oct 21 16:55:17 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 401605 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8AE06140085 for ; Wed, 22 Oct 2014 03:57:01 +1100 (AEDT) Received: from localhost ([::1]:52409 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcjz-00082G-NH for incoming@patchwork.ozlabs.org; Tue, 21 Oct 2014 12:56:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41949) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcj5-0006fE-SF for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xgcj0-0006nw-1I for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:03 -0400 Received: from mail-qc0-f182.google.com ([209.85.216.182]:62312) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgciz-0006nn-UK for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:55:57 -0400 Received: by mail-qc0-f182.google.com with SMTP id i17so1298256qcy.13 for ; Tue, 21 Oct 2014 09:55:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GR31M0sQpZ2BhVuqnNOULgoTb38kNm6vYWCeT2yBjrc=; b=lpcmhwRza8dY1C0h5ujt2PCFAtXXKiVdkbikgMkgBlz3CB/XapwCo8JmsXIhs7z1wD OlnE5hukdok7FGgQ6EgyFg4UTreM87Ezx7+RYFcUXAtYklFJT7sjKvAHK/sCz/7xUlWr ja3D81SMU5J4+aEgycnIcK5lz7gD5cFEiKo7EpskTxUhY2C9GqF43eWhxbKkHkoamvbV VXN7FmuCAAb3rJyx88ef1PZqaHaIrPCSdV8wTla9fMLoOeyKONTVrQz60WTVxoQ+0ypZ JTUjgf6xwNJeDQbhVhp2RD4cnWUeDhjgHnTfN326wdcdCLFyjmOdgc7065hm3XA7tM0M BIvw== X-Gm-Message-State: ALoCoQmzQ0sLAly8gzoXbqGCOrqkdnHd2zHujq+fK9TEgv8+cuAtV3O+3DYEnJgfEXvrGAtR6QaH X-Received: by 10.224.132.72 with SMTP id a8mr24967046qat.37.1413910556637; Tue, 21 Oct 2014 09:55:56 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.55.55 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:55:56 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:17 -0500 Message-Id: <1413910544-20150-6-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.216.182 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 05/32] target-arm: make arm_current_el() return EL3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Make arm_current_el() return EL3 for secure PL1 and monitor mode. Increase MMU modes since mmu_index is directly inferred from arm_ current_el(). Change assertion in arm_el_is_aa64() to allow EL3. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell ========== v6 -> v7 - Fix commit message v5 -> v6 - Rework arm_current_el() logic to properly return EL3 for secure PL1 when EL3 is 32-bit. - Replace direct access of env->aarch64 with is_a64() Signed-off-by: Greg Bellows --- target-arm/cpu.h | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 1138539..cb6ec5c 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -100,7 +100,7 @@ typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, struct arm_boot_info; -#define NB_MMU_MODES 2 +#define NB_MMU_MODES 4 /* We currently assume float and double are IEEE single and double precision respectively. @@ -803,11 +803,12 @@ static inline bool arm_is_secure(CPUARMState *env) /* Return true if the specified exception level is running in AArch64 state. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) { - /* We don't currently support EL2 or EL3, and this isn't valid for EL0 + /* We don't currently support EL2, and this isn't valid for EL0 * (if we're in EL0, is_a64() is what you want, and if we're not in EL0 * then the state of EL0 isn't well defined.) */ - assert(el == 1); + assert(el == 1 || el == 3); + /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This * is a QEMU-imposed simplification which we may wish to change later. * If we in future support EL2 and/or EL3, then the state of lower @@ -996,17 +997,27 @@ static inline bool cptype_valid(int cptype) */ static inline int arm_current_el(CPUARMState *env) { - if (env->aarch64) { + if (is_a64(env)) { return extract32(env->pstate, 2, 2); } - if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { + switch (env->uncached_cpsr & 0x1f) { + case ARM_CPU_MODE_USR: return 0; + case ARM_CPU_MODE_HYP: + return 2; + case ARM_CPU_MODE_MON: + return 3; + default: + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + /* If EL3 is 32-bit then all secure privileged modes run in + * EL3 + */ + return 3; + } + + return 1; } - /* We don't currently implement the Virtualization or TrustZone - * extensions, so EL2 and EL3 don't exist for us. - */ - return 1; } typedef struct ARMCPRegInfo ARMCPRegInfo;