From patchwork Tue Oct 21 16:55:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 401628 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5BA0F14001A for ; Wed, 22 Oct 2014 04:11:30 +1100 (AEDT) Received: from localhost ([::1]:52530 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcy0-0006Wy-3q for incoming@patchwork.ozlabs.org; Tue, 21 Oct 2014 13:11:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42310) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjS-0007Cp-J3 for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XgcjM-000729-Uf for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:26 -0400 Received: from mail-qc0-f169.google.com ([209.85.216.169]:60818) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjM-00071n-Rg for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:20 -0400 Received: by mail-qc0-f169.google.com with SMTP id o8so1320961qcw.14 for ; Tue, 21 Oct 2014 09:56:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dGjZMLKRR51j1IS58t1uajhq9VssGpwSBP/hJv5Xh9E=; b=UQdOH61UVP8+oa99JWZc+UNS24s3tIcOZlEaEjn2cpRZRdH6cYkBRP9Zw3lEbBklkM 3zHwGtcOipCeCiGdnKTmJv5gMQpgUPJHPFcDPvC/IMQ+/Aei7BGtMwvngTyEFcvQMfzi ohcmOALGArfUYN6fBzQQVTuVE+IhAdbbeZibIqvRoGOFmvOEwrAK9B+smqx7Tl3nkJO0 YA4dXMCbcFSNPImQ0e0+Bkj2mAdI5PLttkRLHMGPrjYgXXV+28XULy3oyzJFRwCqjB9H qUV9WinPBOwPCtuu5OhrSKsTi5M6jiUnd+GJ1Sw0jzuAKzCamQ0YggQC5PeYgcFgrbCa ZavQ== X-Gm-Message-State: ALoCoQlln/KR5SaBwlWtk1ZMIl82dhvz90DBWiz6LTcK4se3COn7LbT9UfsUTkt5LeDEYXZ0mZ+e X-Received: by 10.224.61.7 with SMTP id r7mr48467300qah.9.1413910580407; Tue, 21 Oct 2014 09:56:20 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.56.19 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:56:20 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:44 -0500 Message-Id: <1413910544-20150-33-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.216.169 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 63573c6..1e93d7e 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -610,6 +610,7 @@ static void arm1176_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fb767; cpu->reset_fpsid = 0x410120b5; cpu->mvfr0 = 0x11111111; @@ -696,6 +697,7 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fc080; cpu->reset_fpsid = 0x410330c0; cpu->mvfr0 = 0x11110222; @@ -763,6 +765,7 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). @@ -830,6 +833,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_LPAE); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1; cpu->reset_fpsid = 0x410430f0;