From patchwork Tue Oct 21 16:55:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 401618 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 785FE140076 for ; Wed, 22 Oct 2014 04:04:10 +1100 (AEDT) Received: from localhost ([::1]:52468 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcqu-0002tp-AH for incoming@patchwork.ozlabs.org; Tue, 21 Oct 2014 13:04:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42168) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjJ-0006x3-G6 for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XgcjD-0006vv-45 for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:17 -0400 Received: from mail-qg0-f43.google.com ([209.85.192.43]:63749) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjD-0006vl-0J for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:11 -0400 Received: by mail-qg0-f43.google.com with SMTP id j107so1185949qga.2 for ; Tue, 21 Oct 2014 09:56:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pmgtOxyCzmI+COBO8sFc4AqSEP2CEPUTYALBwkdVzsg=; b=mCP2z8IfaIlI4uEtA8/3UgKB2pMWB9du0b8D9f7XJVpFUNHp4hnwtSHGUbc7re3te8 DvIYfhdV72ueHkN3rm3GEyRGljOHfvuV6Vj8drutR/fVwKrLI0VujNTBfZs13in3/mrV 0SaTj0VFr5q1hoEOH2GNAgg+q9KhZxkvxA0Al0HL56U9BbxoH26GPNHV3toi7+RkoEKR SwcI94SKQiRZaDQ0q4/mGHqEg6Zjups5qTl436nOQedwiEEscMOUPH30V1kwQeu5q76W dXpj2YEKTtbQwe3e/cH8oMXY1d0J0Vx1i7U+tIHcrL7Epw0SyOWhfpdxL19iwfYzsUmm Gcig== X-Gm-Message-State: ALoCoQkTT+OQMZ2U4iTIub+7l6L2kDN8b2wXO6WhgaQUjVV7HDoFMnn8faGuc4EftJy7J82veNCX X-Received: by 10.229.86.194 with SMTP id t2mr47509706qcl.20.1413910570631; Tue, 21 Oct 2014 09:56:10 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.56.09 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:56:10 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:33 -0500 Message-Id: <1413910544-20150-22-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.43 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 21/32] target-arm: make CSSELR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Rename CSSELR (cache size selection register) and add secure instance (AArch32). Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ========== v5 -> v6 - Changed _el field variants to be array based - Switch to use distinct CPREG secure flags. - Merged CSSELR and CSSELR_EL1 reginfo entries v4 -> v5 - Changed to use the CCSIDR cpreg bank flag to select the csselr bank instead of the A32_BANKED macro. This more accurately uses the secure state bank matching the CCSIDR. Signed-off-by: Greg Bellows --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 16 ++++++++++++---- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index a46ab7b..8b98c62 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -177,7 +177,15 @@ typedef struct CPUARMState { /* System control coprocessor (cp15) */ struct { uint32_t c0_cpuid; - uint64_t c0_cssel; /* Cache size selection. */ + union { /* Cache size selection */ + struct { + uint64_t _unused_csselr0; + uint64_t csselr_ns; + uint64_t _unused_csselr1; + uint64_t csselr_s; + }; + uint64_t csselr_el[4]; + }; union { /* System control register. */ struct { uint64_t _unused_sctlr; diff --git a/target-arm/helper.c b/target-arm/helper.c index 6a7c112..a8fe482 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -789,7 +789,14 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = arm_env_get_cpu(env); - return cpu->ccsidr[env->cp15.c0_cssel]; + + /* Acquire the CSSELR index from the bank corresponding to the CCSIDR + * bank + */ + uint32_t index = A32_BANKED_REG_GET(env, csselr, + ARM_CP_SECSTATE_TEST(ri, ARM_CP_SECSTATE_S)); + + return cpu->ccsidr[index]; } static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -915,9 +922,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, - .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel), - .writefn = csselr_write, .resetvalue = 0 }, + .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, + .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), + offsetof(CPUARMState, cp15.csselr_ns) } }, /* Auxiliary ID register: this actually has an IMPDEF value but for now * just RAZ for all cores: */