From patchwork Tue Oct 21 16:55:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 401622 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5BFA414007F for ; Wed, 22 Oct 2014 04:07:29 +1100 (AEDT) Received: from localhost ([::1]:52491 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcu7-000835-0V for incoming@patchwork.ozlabs.org; Tue, 21 Oct 2014 13:07:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42092) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjD-0006ns-Ve for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xgcj9-0006sw-1S for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:11 -0400 Received: from mail-qg0-f41.google.com ([209.85.192.41]:35789) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcj8-0006sg-SL for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:06 -0400 Received: by mail-qg0-f41.google.com with SMTP id a108so1203533qge.28 for ; Tue, 21 Oct 2014 09:56:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8yi2xcuc3Qrg/b8WNsMX2dwCJloE2sd9dep+UOUwzWo=; b=UUVx8GkWlO812Z07t/HeU9bt7JklGvtkeQnkLlgpSGNkOIs9RVtm4ms9v6/Lzu0oVL YvhfB1I5B8i9DdVWuyouYFXTtKTJB1B3skQ/eH4QGVL/Do3ZYRp1zVxrpqONCJV2jq91 ifO1tpdLRIngHiTsNYAJjQbVlGm8T64vqSTEUB64Q4oJHVQOvKB3e9oan7+I7EB41GS4 /DzIaTeDf+qUbHFh38qopf4wMKXO2h9oNOzABrbtckjIsKzAGzwwwNuBlUgTIwxpJpRh P0eTxG/fjaf8iv9MPjhVXzFmqt6Gre6vG1ldbcX5uMLl2SmrCWMeyFYrxBVXVZN/OfqK f5Tg== X-Gm-Message-State: ALoCoQmmlxkbjOadsGntw4vKRe0Gj39ZL4oEUCy9yW/NexRmZaHoYuwWUysDoBi8OoC9DgtkvLvO X-Received: by 10.140.81.210 with SMTP id f76mr44883563qgd.60.1413910565663; Tue, 21 Oct 2014 09:56:05 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.56.04 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:56:05 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:27 -0500 Message-Id: <1413910544-20150-16-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.41 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 15/32] target-arm: implement IRQ/FIQ routing to Monitor mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index bc82951..a22fcb2 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4212,12 +4212,21 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Disable IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I; offset = 4; + if (env->cp15.scr_el3 & SCR_IRQ) { + /* IRQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + mask |= CPSR_F; + } break; case EXCP_FIQ: new_mode = ARM_CPU_MODE_FIQ; addr = 0x1c; /* Disable FIQ, IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I | CPSR_F; + if (env->cp15.scr_el3 & SCR_FIQ) { + /* FIQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + } offset = 4; break; case EXCP_SMC: