From patchwork Tue Oct 21 16:55:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 401616 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7265014007F for ; Wed, 22 Oct 2014 04:03:51 +1100 (AEDT) Received: from localhost ([::1]:52464 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcqb-0002QT-Ib for incoming@patchwork.ozlabs.org; Tue, 21 Oct 2014 13:03:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42046) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjA-0006kJ-SC for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xgcj5-0006qn-HW for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:08 -0400 Received: from mail-qg0-f53.google.com ([209.85.192.53]:52721) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcj5-0006qd-Da for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:03 -0400 Received: by mail-qg0-f53.google.com with SMTP id q107so1207063qgd.12 for ; Tue, 21 Oct 2014 09:56:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cG8BUquac5N6HfqMiT3uXy5hZENFDXucdtfxp7yG4To=; b=XCAX8EurJKNvkK1dO2V2Kd1FrjmfES1KNwo0pzhfEUfVFy8URLPLhl5iYh4psB8Uy/ 251oNitbaW5oJMl1CYwWWXeQIzTecAazwYrAuLq6oXopK2gxTUBbmnpov0qFb4D9XwJR 5RDutlayo/DaJtWG6r0fH9ZuzTfsMM6LvGBcgkqj5ld/3d96bxQv2g7UFzvw2aHkc8S3 hKoRfd5zfnXO6afbTAKp6s8Qfr51j/8ByAWeA0aMXb4vupDL2jN0K1r1Qe2W1mAu6sum /uQHVGaT+DqnrnMz8euij3z+V2T+e89Y/zNwvHKo1jXHojAodVtL1wNEGn1CG361Jbis cCVw== X-Gm-Message-State: ALoCoQmySg4ZiRNiXnCITEtFbC8IJMI5smz/ir5Ls1MaoV3pTjfQVqWTqG2SMxB0u6Fyip9ilJgm X-Received: by 10.229.124.9 with SMTP id s9mr47715844qcr.15.1413910562157; Tue, 21 Oct 2014 09:56:02 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.56.01 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:56:01 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:23 -0500 Message-Id: <1413910544-20150-12-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.53 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 11/32] target-arm: add CPREG secure state support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ========== v6 -> v7 - Add naming for fieldoffset fields and macros for accessing. This was needed to overcome issues with the GCC-4.4 compiler. v5 -> v6 - Separate out secure CPREG flags - Add convenience macro for testing flags - Removed extraneous newline - Move add_cpreg_to_hashtable() functionality to a later commit for which it is dependent on. - Added comment explaining fieldoffset padding v4 -> v5 - Added ARM CP register secure and non-secure bank flags - Added setting of secure and non-secure flags furing registration Signed-off-by: Greg Bellows --- target-arm/cpu.h | 50 +++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index e041437..786deac 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -990,6 +990,24 @@ enum { ARM_CP_STATE_BOTH = 2, }; +/* ARM CP register secure state flags. These flags identify security state + * attributes for a given CP register entry. + * The existence of both or neither secure and non-secure flags indicates that + * the register has both a secure and non-secure hash entry. A single one of + * these flags causes the register to only be hashed for the specified + * security state. + * Although definitions may have any combination of the S/NS bits, each + * registered entry will only have one to identify whether the entry is secure + * or non-secure. + */ +enum { + ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ + ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ +}; + +/* Convenience macro for checking for a specific bit */ +#define ARM_CP_SECSTATE_TEST(_ri, _flag) (((_ri)->secure & (_flag)) == (_flag)) + /* Return true if cptype is a valid type field. This is used to try to * catch errors where the sentinel has been accidentally left off the end * of a list of registers. @@ -1124,6 +1142,8 @@ struct ARMCPRegInfo { int type; /* Access rights: PL*_[RW] */ int access; + /* Security state: ARM_CP_SECSTATE_* bits/values */ + int secure; /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when * this register was defined: can be used to hand data through to the * register read/write functions, since they are passed the ARMCPRegInfo*. @@ -1133,12 +1153,36 @@ struct ARMCPRegInfo { * fieldoffset is non-zero, the reset value of the register. */ uint64_t resetvalue; - /* Offset of the field in CPUARMState for this register. This is not - * needed if either: + /* Offsets of the fields (secure/non-secure) in CPUARMState for this + * register. The array will be accessed by the ns bit which means the + * secure instance has to be at [0] while the non-secure instance must be + * at [1]. If a register is not banked .fieldoffset can be used, which maps + * to the non-secure bank. + * + * Extra padding is added to align the default fieldoffset field with the + * non-secure bank_fieldoffsets entry. This is necessary for maintaining + * the same storage offset when AArch64 and banked AArch32 are seperately + * defined. + * + * This is not needed if either: * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs * 2. both readfn and writefn are specified */ - ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ + union { /* offsetof(CPUARMState, field) */ + struct { + ptrdiff_t _fieldoffset_padding; + ptrdiff_t fieldoffset; + } _fieldoffset_s; + ptrdiff_t bank_fieldoffsets[2]; + } _fieldoffset_u; + +/* + * GCC-4.4 can't handle the anonymous union/struct combos, so we'll add names + * along with macros for short-cutting the field names. + */ +#define bank_fieldoffsets _fieldoffset_u.bank_fieldoffsets +#define fieldoffset _fieldoffset_u._fieldoffset_s.fieldoffset + /* Function for making any access checks for this register in addition to * those specified by the 'access' permissions bits. If NULL, no extra * checks required. The access check is performed at runtime, not at