From patchwork Fri Oct 10 16:03:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 398702 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BF37A14009B for ; Sat, 11 Oct 2014 03:07:46 +1100 (EST) Received: from localhost ([::1]:49403 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XccjI-0004CI-Ja for incoming@patchwork.ozlabs.org; Fri, 10 Oct 2014 12:07:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34981) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfo-0006qL-Ko for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xccfj-00080C-Cw for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:08 -0400 Received: from mail-oi0-f42.google.com ([209.85.218.42]:57741) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfj-0007zw-7p for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:03 -0400 Received: by mail-oi0-f42.google.com with SMTP id a141so7149174oig.15 for ; Fri, 10 Oct 2014 09:04:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=TK1rEpun5cixy9EVxddc0sI7gddEwJcArHRGiJLMV1g=; b=bDrgssmPqZxsNldgdn71pplc+TMXysxf0Yt1VvZoQPK9Q1rqC7O36D+tx+mPVttQul iV5xfQfX9iz1o23FUWWC5Td7Dsjvy9pkz/leJeg9OsqXxefjttSVAf7nmCk1nPCzNz08 uB2L7WW7KsQeZyNOk3QMR+hfJPb34joHUSLcTJ9jLATGL5BcjuChRjYrfOfzBO+SlSHt Qz16YwJd3R4VlvKHHIAYV1k6I4uk48xjXF+9EBQvsH7lZ6rfuy25XcT0SdenrI0m76Ye Jc+Rnl+kqXzhCUWJ3VNBF8T6Bp4GsHCUyIKg0FaMVB+zR38ZIfWSnZBYv8ldqezUIaFS P+mQ== X-Gm-Message-State: ALoCoQkd4Mt3tp3n9m1gFckJU+B7j+K1t+kgyz3NZugIJ21vJlU12On0GU5kOTkou7UNekbNVVk9 X-Received: by 10.202.204.198 with SMTP id c189mr2724939oig.81.1412957042836; Fri, 10 Oct 2014 09:04:02 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id d6sm5382455obt.12.2014.10.10.09.04.01 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 10 Oct 2014 09:04:02 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Fri, 10 Oct 2014 11:03:19 -0500 Message-Id: <1412957023-11105-9-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> References: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.218.42 Subject: [Qemu-devel] [PATCH v6 08/32] target-arm: add async excp target_el function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Adds a dedicated function for IRQ and FIQ exceptions to determine target_el and mode (AArch32) according to tables in ARM ARMv8 and ARM ARM v7. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ========== v5 -> v6 - Removed unneeded arm_phys_excp_target_el() function prototype. - Removed unneeded arm_phys_excp_target_el() USER_ONLY function. - Fixed up arm_phys_excp_target_el() function definition to be static. - Globally replace Aarch# with AArch# v4 -> v5 - Simplify target EL function including removal of mode which was unused - Merged with patch that plugs in the use of the function v3 -> v4 - Fixed arm_phys_excp_target_el() 0/0/0 case to return excp_mode when EL<2 rather than ABORT. --- target-arm/helper.c | 97 ++++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 77 insertions(+), 20 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 7f3f049..9910f72 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3767,6 +3767,80 @@ void switch_mode(CPUARMState *env, int mode) } /* + * Determine the target EL for physical exceptions + */ +static inline uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, + uint32_t cur_el, bool secure) +{ + CPUARMState *env = cs->env_ptr; + uint32_t target_el = 1; + + /* There is no SCR or HCR routing unless the respective EL3 and EL2 + * extensions are supported. This initial setting affects whether any + * other conditions matter. + */ + bool scr_routing = arm_feature(env, ARM_FEATURE_EL3); /* IRQ, FIQ, EA */ + bool hcr_routing = arm_feature(env, ARM_FEATURE_EL2); /* IMO, FMO, AMO */ + + /* Fast-path if EL2 and EL3 are not enabled */ + if (!scr_routing && !hcr_routing) { + return target_el; + } + + switch (excp_idx) { + case EXCP_IRQ: + scr_routing &= ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); + hcr_routing &= ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO); + break; + case EXCP_FIQ: + scr_routing &= ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); + hcr_routing &= ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO); + } + + /* If SCR routing is enabled we always go to EL3 regardless of EL3 + * execution state + */ + if (scr_routing) { + /* IRQ|FIQ|EA == 1 */ + return 3; + } + + /* If HCR.TGE is set all exceptions that would be routed to EL1 are + * routed to EL2 (in non-secure world). + */ + hcr_routing &= (env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE; + + /* Determine target EL according to ARM ARMv8 tables G1-15 and G1-16 */ + if (arm_el_is_aa64(env, 3)) { + /* EL3 in AArch64 */ + if (!secure) { + /* If non-secure, we may route to EL2 depending on other state. + * If we are coming from the secure world then we always route to + * EL1. + */ + if (hcr_routing || + (cur_el == 2 && !(env->cp15.scr_el3 & SCR_RW))) { + /* If HCR.FMO/IMO is set or we already in EL2 and it is not + * configured to be AArch64 then route to EL2. + */ + target_el = 2; + } + } + } else { + /* EL3 in AArch32 */ + if (secure) { + /* If coming from secure always route to EL3 */ + target_el = 3; + } else if (hcr_routing || cur_el == 2) { + /* If HCR.FMO/IMO is set or we are already EL2 then route to EL2 */ + target_el = 2; + } + } + + return target_el; +} + +/* * Determine the target EL for a given exception type. */ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) @@ -3774,14 +3848,8 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; unsigned int cur_el = arm_current_el(env); - unsigned int target_el; - /* FIXME: Use actual secure state. */ - bool secure = false; - - if (!env->aarch64) { - /* TODO: Add EL2 and 3 exception handling for AArch32. */ - return 1; - } + unsigned int target_el = 1; + bool secure = arm_is_secure(env); switch (excp_idx) { case EXCP_HVC: @@ -3793,19 +3861,8 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) break; case EXCP_FIQ: case EXCP_IRQ: - { - const uint64_t hcr_mask = excp_idx == EXCP_FIQ ? HCR_FMO : HCR_IMO; - const uint32_t scr_mask = excp_idx == EXCP_FIQ ? SCR_FIQ : SCR_IRQ; - - target_el = 1; - if (!secure && (env->cp15.hcr_el2 & hcr_mask)) { - target_el = 2; - } - if (env->cp15.scr_el3 & scr_mask) { - target_el = 3; - } + target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); break; - } case EXCP_VIRQ: case EXCP_VFIQ: target_el = 1;