From patchwork Fri Oct 10 16:03:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 398728 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 138F4140076 for ; Sat, 11 Oct 2014 03:27:52 +1100 (EST) Received: from localhost ([::1]:49667 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xcd2k-0004iW-3y for incoming@patchwork.ozlabs.org; Fri, 10 Oct 2014 12:27:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35321) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XccgC-0007Xu-Bm for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xccg6-0008BU-NW for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:32 -0400 Received: from mail-oi0-f47.google.com ([209.85.218.47]:52164) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccg6-0008BO-IN for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:26 -0400 Received: by mail-oi0-f47.google.com with SMTP id a141so7291201oig.20 for ; Fri, 10 Oct 2014 09:04:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=LkkxSPKTljX4i8EZp9mIV4TuG1GwNCW55PclEMjHP6I=; b=OBEGGG8Cfd/iRGqEYLmZzQG85C0KXRswNXMaL8WkcTkGkPdnVEQ1ilpEDgrVeJXQw/ A01yFitJXeyr0++qDQVJtpsYZguxNH3/MYLG1t9XDcZSZoC/CJiBr5Zr1e0532iWT5AJ +bu1Z6AMsZTJ+UkWQMWG4zvfxVs6W0uTQVBWV4tC4IjZ5EDYz8RWFLJmSSPFjjy8S19g 7okrtP0ZelVNcTbX7/wpX09dwzJ1m6jFGhn8yadW4Dp/J70K1jUHjkMfK0tNUcPJJegG UGs7QmwkWHCsYT4GMcZ/KF1DOpLicgIeJ4nQNNaLk0cuDOh0WHD4s8Ra+Jj7AUsWnt3P gfEg== X-Gm-Message-State: ALoCoQm3wZv/Z96Zgoj7TlvD5sDjghIrz63TriBCzeQD7OAAZT4o3wA6Hw0cYQO4iylD67/RbgOq X-Received: by 10.182.79.65 with SMTP id h1mr3177363obx.53.1412957066184; Fri, 10 Oct 2014 09:04:26 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id d6sm5382455obt.12.2014.10.10.09.04.25 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 10 Oct 2014 09:04:25 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Fri, 10 Oct 2014 11:03:43 -0500 Message-Id: <1412957023-11105-33-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> References: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.218.47 Subject: [Qemu-devel] [PATCH v6 32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 8ba72ed..fa12602 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -601,6 +601,7 @@ static void arm1176_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fb767; cpu->reset_fpsid = 0x410120b5; cpu->mvfr0 = 0x11111111; @@ -687,6 +688,7 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fc080; cpu->reset_fpsid = 0x410330c0; cpu->mvfr0 = 0x11110222; @@ -754,6 +756,7 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). @@ -821,6 +824,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_LPAE); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1; cpu->reset_fpsid = 0x410430f0;