From patchwork Fri Oct 10 16:03:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 398701 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0267D1400AB for ; Sat, 11 Oct 2014 03:07:40 +1100 (EST) Received: from localhost ([::1]:49400 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XccjC-00041q-1I for incoming@patchwork.ozlabs.org; Fri, 10 Oct 2014 12:07:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35169) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfz-0007A8-Br for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xccfr-00084q-TF for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:19 -0400 Received: from mail-oi0-f46.google.com ([209.85.218.46]:53348) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfr-00084j-OW for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:11 -0400 Received: by mail-oi0-f46.google.com with SMTP id h136so7036288oig.33 for ; Fri, 10 Oct 2014 09:04:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=s2aAmKXqZXrhtDGq64tWx8MLeXgLt9OqqUbovNPx+i8=; b=fyjUHvlcv78TEx7hcvuSVJevEaleozUOtuLlv9rw6sQYPB6K8820LnqjbCxulCl1uR 6b+VlHEBIto8BzyLXoZL8woVi0Yv414dkLTVgJ98/E/z45YahWi5VE/IV99Fwu1vpjf7 m+9XNAgMOjF89mxhQaUDRKCzR3quO34ij/Lg4MQLXEbmPgWqLKefpfDmFV8B5MOSQe/1 WvxULzP6DrkGzoULDQ+k266PPxFawYBsDXDTom5w2YQ7U1CvB0uB5+jxuK/OiFVLivXM CZAs8e20va/jReksGuaoa5H/X9UeuhuMLHqq5tAbraq12SG9LD279lTvoaTjU9Jq+bKq lRHA== X-Gm-Message-State: ALoCoQmemjRbWafub0hmEesDuS96pOc5f0jSBxt4Bbk3sXujLQ91iYB4FKUpNF0VV53EWBKYpmRi X-Received: by 10.182.87.102 with SMTP id w6mr5529145obz.35.1412957051393; Fri, 10 Oct 2014 09:04:11 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id d6sm5382455obt.12.2014.10.10.09.04.10 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 10 Oct 2014 09:04:10 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Fri, 10 Oct 2014 11:03:28 -0500 Message-Id: <1412957023-11105-18-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> References: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.218.46 Subject: [Qemu-devel] [PATCH v6 17/32] target-arm: add NSACR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Implements NSACR register with corresponding read/write functions for ARMv7 and ARMv8. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ---------- v4 -> v5 - Changed to use renamed arm_current_el() --- target-arm/cpu.h | 6 +++++ target-arm/helper.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 73 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 8ab3576..4d9f6f8 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -181,6 +181,7 @@ typedef struct CPUARMState { uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ + uint32_t c1_nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ uint64_t c2_control; /* MMU translation table base control. */ @@ -634,6 +635,11 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) +#define NSACR_NSTRCDIS (1U << 20) +#define NSACR_RFR (1U << 19) +#define NSACR_NSASEDIS (1U << 15) +#define NSACR_NSD32DIS (1U << 14) + /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); diff --git a/target-arm/helper.c b/target-arm/helper.c index 6d0f3ec..384af14 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -520,7 +520,19 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, /* VFP coprocessor: cp10 & cp11 [23:20] */ mask |= (1 << 31) | (1 << 30) | (0xf << 20); - if (!arm_feature(env, ARM_FEATURE_NEON)) { + if (arm_feature(env, ARM_FEATURE_NEON)) { + /* NSACR can disable non-secure writes to + * ASEDIS [31] or D32DIS [30] + */ + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env)) { + if ((env->cp15.c1_nsacr & NSACR_NSASEDIS)) { + mask &= ~(1 << 31); + } + if ((env->cp15.c1_nsacr & NSACR_NSD32DIS)) { + mask &= ~(1 << 30); + } + } + } else { /* ASEDIS [31] bit is RAO/WI */ value |= (1 << 31); } @@ -532,6 +544,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, !arm_feature(env, ARM_FEATURE_VFP3)) { /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ value |= (1 << 30); + mask |= (1 << 30); } } value &= mask; @@ -2310,6 +2323,55 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { REGINFO_SENTINEL }; +static void nsacr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint32_t mask = 0; + + /* Pre ARMv8 some bits are RAO or UNK/SBZP */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + + if (arm_feature(env, ARM_FEATURE_VFP)) { + mask |= NSACR_NSASEDIS | NSACR_NSD32DIS; + + if (!arm_feature(env, ARM_FEATURE_NEON)) { + /* NSASEDIS are RAO/WI */ + value |= NSACR_NSASEDIS; + } + + /* VFPv3 and upwards with NEON implement 32 double precision + * registers (D0-D31). + */ + if (!arm_feature(env, ARM_FEATURE_NEON) || + !arm_feature(env, ARM_FEATURE_VFP3)) { + /* NSD32DIS is RAO/WI if D16-31 are not implemented. */ + value |= NSACR_NSD32DIS; + } + } + + /* cpn bits [13:0] */ + mask = 0x3fff; + + value &= mask; + } + + raw_write(env, ri, value); +} + +static uint64_t nsacr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t ret = raw_read(env, ri); + + if (arm_feature(env, ARM_FEATURE_V8)) { + if (!arm_feature(env, ARM_FEATURE_EL3) || ( + arm_el_is_aa64(env, 3) && !is_a64(env) && + arm_current_el(env) != 3)) { + ret = 0x0000C00; + } + } + return ret; +} + static const ARMCPRegInfo v8_el3_cp_reginfo[] = { { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, @@ -2347,6 +2409,10 @@ static const ARMCPRegInfo v7_el3_cp_reginfo[] = { { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), .resetvalue = 0, .writefn = scr_write}, + { .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2, + .access = PL3_RW | PL1_R, .resetvalue = 0, + .writefn = nsacr_write, .readfn = nsacr_read, + .fieldoffset = offsetof(CPUARMState, cp15.c1_nsacr) }, REGINFO_SENTINEL };