From patchwork Fri Oct 10 16:03:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 398712 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6B171140092 for ; Sat, 11 Oct 2014 03:14:05 +1100 (EST) Received: from localhost ([::1]:49487 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XccpP-0006Nu-Ef for incoming@patchwork.ozlabs.org; Fri, 10 Oct 2014 12:14:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35013) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfp-0006sL-RU for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xccfk-00080V-90 for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:09 -0400 Received: from mail-oi0-f53.google.com ([209.85.218.53]:56848) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfk-00080M-3Y for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:04 -0400 Received: by mail-oi0-f53.google.com with SMTP id v63so7031259oia.40 for ; Fri, 10 Oct 2014 09:04:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=aZA8xFfGPCoytZCDVs6xLaGtg7fUcoVxG/RWSmXn7S0=; b=J9/sXXo47ovK9FXFXdSpsiaimefCLGUZ6Ayiri36TQJH+ixD4bWilmpvPh9sHkTbUc dRAa0a7gAsT02gAz0DKXNKZFA9P0d4j8Zh1aQ4cSO+9xIASGBHPYcXMMXZzQeU69c31H 4YGMydpyXf0JwaCrv1eOOvfuGBaCfdabAcyxH0oEnnoLCKm8p+w2qawrj7u0+VKWPBLj szb76LvSiryrTTQfT/3kMhN6GJJsI+NJiY+jQ+CMtHMqbD0zKXrZKBeqHxebWpetE+ba slYw/pV0NtjscZXzkevWoRRqRhCD8VyAu/mNutI3xdRuHl6fyt0cACoDniofzuqfKpIa Cc1A== X-Gm-Message-State: ALoCoQnc42UzL/7i1UzEltj9/zeOqd5xYL1Bvds4vPBU1N0+UZI6yJqm4GrttWBMuN+bIErTAIPW X-Received: by 10.202.171.194 with SMTP id u185mr5299535oie.24.1412957043766; Fri, 10 Oct 2014 09:04:03 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id d6sm5382455obt.12.2014.10.10.09.04.02 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 10 Oct 2014 09:04:03 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Fri, 10 Oct 2014 11:03:20 -0500 Message-Id: <1412957023-11105-10-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> References: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.218.53 Subject: [Qemu-devel] [PATCH v6 09/32] target-arm: add banked register accessors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler If EL3 is in AArch32 state certain cp registers are banked (secure and non-secure instance). When reading or writing to coprocessor registers the following macros can be used. - A32_BANKED macros are used for choosing the banked register based on provided input security argument. This macro is used to choose the bank during translation of MRC/MCR instructions that are dependent on something other than the current secure state. - A32_BANKED_CURRENT macros are used for choosing the banked register based on current secure state. This is NOT to be used for choosing the bank used during translation as it breaks monitor mode. If EL3 is operating in AArch64 state coprocessor registers are not banked anymore. The macros use the non-secure instance (_ns) in this case, which is architecturally mapped to the AArch64 EL register. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ========== v5 -> v6 - Converted macro USE_SECURE_REG() into inlince function use_secure_reg() - Globally replace Aarch# with AArch# v4 -> v5 - Cleaned-up macros to try and alleviate misuse. Made A32_BANKED macros take secure arg indicator rather than relying on USE_SECURE_REG. Incorporated the A32_BANKED macros into the A32_BANKED_CURRENT. CURRENT is now the only one that automatically chooses based on current secure state. --- target-arm/cpu.h | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6e633cd..9f1613f 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -812,6 +812,46 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return arm_feature(env, ARM_FEATURE_AARCH64); } +/* Function for determing whether to use the secure or non-secure bank of a CP + * register. When EL3 is operating in AArch32 state, the NS-bit determines + * whether the secure instance of a cp-register should be used. + */ +static inline bool use_secure_reg(CPUARMState *env) +{ + bool ret = (arm_feature(env, ARM_FEATURE_EL3) && + !arm_el_is_aa64(env, 3) && + !(env->cp15.scr_el3 & SCR_NS)); + + return ret; +} + +/* Macros for accessing a specified CP register bank */ +#define A32_BANKED_REG_GET(_env, _regname, _secure) \ + ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) + +#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ + do { \ + if (_secure) { \ + (_env)->cp15._regname##_s = (_val); \ + } else { \ + (_env)->cp15._regname##_ns = (_val); \ + } \ + } while (0) + +/* Macros for automatically accessing a specific CP register bank depending on + * the current secure state of the system. These macros are not intended for + * supporting instruction translation reads/writes as these are dependent + * solely on the SCR.NS bit and not the mode. + */ +#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ + A32_BANKED_REG_GET((_env), _regname, \ + ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env)))) + +#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ + A32_BANKED_REG_SET((_env), _regname, \ + ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))), \ + (_val)) + void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx);