From patchwork Wed Oct 8 18:25:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 397684 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 00D891400B2 for ; Thu, 9 Oct 2014 05:44:50 +1100 (EST) Received: from localhost ([::1]:37793 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xbvwc-0005yw-Mj for incoming@patchwork.ozlabs.org; Wed, 08 Oct 2014 14:26:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35852) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XbvwC-0005S1-AF for qemu-devel@nongnu.org; Wed, 08 Oct 2014 14:26:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xbvw5-0002vM-B0 for qemu-devel@nongnu.org; Wed, 08 Oct 2014 14:26:12 -0400 Received: from mail-pa0-f48.google.com ([209.85.220.48]:38819) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xbvw5-0002vF-5W for qemu-devel@nongnu.org; Wed, 08 Oct 2014 14:26:05 -0400 Received: by mail-pa0-f48.google.com with SMTP id eu11so9418189pac.7 for ; Wed, 08 Oct 2014 11:26:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UN4Q1ZWU1Ce7gaaExHuFc8tNZJO+YHVqgjO3ShZWYkk=; b=VcPs1nHjYNYIF/R7u42hT9ot/V0YoG9rRShJ0cotfvZG/D/LbsPBK7HgOgoXfOTWLB JbPw4z9ygxEncloJ9xwCsdzO46b3UEsutpfXule6eU3FLdjJ3vHLRoClAHUyc09e6gK7 +BOc7C8JhvF7OB0g83VnmJulSaIjUdqB+a1vkOKSzE0GrHaITZ5LrdYLFqFWeECZrIf7 0dctr395+33r1h/rXmGmu4jK5WP14SxWrXiOqsrlGTEdWTRo1r0uYBRUs72khp7QzFzq KSV0cjBwBXNP95464kvjnTm0EYbrjEbn5Giw5VpvmKCl7I7phEpiqxizi85B1D5rw97Q /2CA== X-Gm-Message-State: ALoCoQmrN05iovyVzPO66ZIeTzHCOUyHaFqqnUHpLwtQ7H8J5cJicQyU3m7kqktU0OUwyNRLKc1r X-Received: by 10.66.66.193 with SMTP id h1mr12923436pat.93.1412792764441; Wed, 08 Oct 2014 11:26:04 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id fn4sm639997pab.39.2014.10.08.11.26.03 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 08 Oct 2014 11:26:03 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 8 Oct 2014 13:25:43 -0500 Message-Id: <1412792743-30906-2-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412792743-30906-1-git-send-email-greg.bellows@linaro.org> References: <1412792743-30906-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.48 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH] target-arm: add second UART to virt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Added UART1 to virt to enable separate UARTs for secure/nonsecure worlds. Signed-off-by: Greg Bellows --- hw/arm/virt.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 8c6b171..0740cdc 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -64,7 +64,8 @@ enum { VIRT_CPUPERIPHS, VIRT_GIC_DIST, VIRT_GIC_CPU, - VIRT_UART, + VIRT_UART0, + VIRT_UART1, VIRT_MMIO, VIRT_RTC, }; @@ -104,8 +105,9 @@ static const MemMapEntry a15memmap[] = { /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, - [VIRT_UART] = { 0x09000000, 0x00001000 }, - [VIRT_RTC] = { 0x09010000, 0x00001000 }, + [VIRT_UART0] = { 0x09000000, 0x00001000 }, + [VIRT_UART1] = { 0x09010000, 0x00001000 }, + [VIRT_RTC] = { 0x09020000, 0x00001000 }, [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ /* 0x10000000 .. 0x40000000 reserved for PCI */ @@ -113,8 +115,9 @@ static const MemMapEntry a15memmap[] = { }; static const int a15irqmap[] = { - [VIRT_UART] = 1, - [VIRT_RTC] = 2, + [VIRT_UART0] = 1, + [VIRT_UART1] = 2, + [VIRT_RTC] = 3, [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ }; @@ -352,12 +355,12 @@ static void create_gic(const VirtBoardInfo *vbi, qemu_irq *pic) fdt_add_gic_node(vbi); } -static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic) +static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic, int uart) { char *nodename; - hwaddr base = vbi->memmap[VIRT_UART].base; - hwaddr size = vbi->memmap[VIRT_UART].size; - int irq = vbi->irqmap[VIRT_UART]; + hwaddr base = vbi->memmap[uart].base; + hwaddr size = vbi->memmap[uart].size; + int irq = vbi->irqmap[uart]; const char compat[] = "arm,pl011\0arm,primecell"; const char clocknames[] = "uartclk\0apb_pclk"; @@ -589,7 +592,8 @@ static void machvirt_init(MachineState *machine) create_gic(vbi, pic); - create_uart(vbi, pic); + create_uart(vbi, pic, VIRT_UART0); + create_uart(vbi, pic, VIRT_UART1); create_rtc(vbi, pic);