From patchwork Tue Sep 30 21:49:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 395354 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3251F14012B for ; Wed, 1 Oct 2014 08:11:56 +1000 (EST) Received: from localhost ([::1]:46820 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5eE-0000x3-59 for incoming@patchwork.ozlabs.org; Tue, 30 Sep 2014 18:11:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43548) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5Jy-0001Ds-I3 for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:51:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZ5Jp-00043h-Qk for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:58 -0400 Received: from mail-pa0-f42.google.com ([209.85.220.42]:46659) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5Jo-00042s-Ny for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:49 -0400 Received: by mail-pa0-f42.google.com with SMTP id et14so2542506pad.15 for ; Tue, 30 Sep 2014 14:50:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rJmau8OsI+tXn0fZsRLQP/AkbbcEdmGX0wqK4F16bHA=; b=LhHtLwx6vuofnlqLyPt/hwcjF+JlKnuOukToWsImaURFsRvzJuYpdyYSqjIwzB6RUG tWZa7I/oIoKuwwFW8902R2IVGzxBsuj1xa7L1MWaXqkVy9/PBwegKzz2NKHHsIzWLCny 0yvQhNb60O1dc0J4q+tgi4CZXHJkZuc6F5Sd95d4fXQV2sNMyTfvrrErWiY/uHh00tr6 MLdPLDSUmvM8NkqSlHPLvvFVeeYLZqfZ93K1Y4X1BIeXSVqcPUkDTihw3Synviv+zn4m xP7VmrWWQ/0/iBZh5sN2nvcA9PVQ1899+nfOiH2TNBeAZ7IHr8/pbRxak38LgISgh4Y5 sZYw== X-Gm-Message-State: ALoCoQndkYS+yqJSvqmZWQGtJbpfl5KAvupxJ5cwwQImQZu5TXFqe/BvsoQh56lrnbQGkcJkaOOC X-Received: by 10.68.175.99 with SMTP id bz3mr73717415pbc.112.1412113844600; Tue, 30 Sep 2014 14:50:44 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id qy1sm16027662pbc.27.2014.09.30.14.50.43 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 30 Sep 2014 14:50:43 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 30 Sep 2014 16:49:45 -0500 Message-Id: <1412113785-21525-34-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.42 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v5 33/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index ea2169b..2a0eeb3 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -601,6 +601,7 @@ static void arm1176_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fb767; cpu->reset_fpsid = 0x410120b5; cpu->mvfr0 = 0x11111111; @@ -687,6 +688,7 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fc080; cpu->reset_fpsid = 0x410330c0; cpu->mvfr0 = 0x11110222; @@ -754,6 +756,7 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). @@ -821,6 +824,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_LPAE); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1; cpu->reset_fpsid = 0x410430f0;