From patchwork Tue Sep 30 21:49:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 395347 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C84AF14012B for ; Wed, 1 Oct 2014 08:05:59 +1000 (EST) Received: from localhost ([::1]:46661 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5YT-0000cO-GL for incoming@patchwork.ozlabs.org; Tue, 30 Sep 2014 18:05:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43587) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5Jz-0001F4-FF for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:51:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZ5Jt-00044r-2p for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:59 -0400 Received: from mail-pa0-f43.google.com ([209.85.220.43]:58271) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5Js-00041E-92 for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:52 -0400 Received: by mail-pa0-f43.google.com with SMTP id hz1so7110477pad.16 for ; Tue, 30 Sep 2014 14:50:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RlGaUs8nLhxf9T3n0lPHWYtgWf8DvUVePMKPRgeIpv8=; b=KJ8oxAziHXGIiQ8Lyu9CLLPl6Nmhxv/GtJcdO9tPMj8PzpKkXGTPeJROa7QIzfgxXJ nMQj7yhsNnPLSrqabboWDECg5gq0aD6iGG5v6WXAkIel6rrX5rlOjOWO1sMib9wPYjsc o7y9NoSEXz1Jb9aChOiE0v5yENuO8g5/QLs7ScsXFi0Xie8g62E3J4XqQXB0rrefZ8nm HTErdNo0oEZOcMr1mS/tkFws0Q7CoU3hXYCqCwUgQz9OKhJkVfq8pCvKlmAMfM+x9XwX gt/JycSzXjF/NVCuPBPb9tk+RmhDNR1icCa6a2q/aTh57qLUlUxIqwcTcxBUaM131hOv umVA== X-Gm-Message-State: ALoCoQnnaABYIUMhXFGPQcpR1ko+hWuY6vwvT9SNiOq2fYRYbnjxWicPoLRLHD7qLGWrkx9r/TF4 X-Received: by 10.68.96.4 with SMTP id do4mr73836245pbb.44.1412113838947; Tue, 30 Sep 2014 14:50:38 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id qy1sm16027662pbc.27.2014.09.30.14.50.37 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 30 Sep 2014 14:50:38 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 30 Sep 2014 16:49:41 -0500 Message-Id: <1412113785-21525-30-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.43 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v5 29/33] target-arm: make VBAR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) VBAR has a secure and a non-secure instance, which are mapped to VBAR_EL1 and VBAR_EL3. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ---------------- v3 -> v4 - Fix vbar union/structure definition - Revert back to array-based vbar definition combined with v7 naming --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 13 +++++++++---- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 4b70530..1fa9e0d 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -311,7 +311,15 @@ typedef struct CPUARMState { uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; - uint64_t vbar_el[4]; /* vector base address register */ + union { /* vector base address register */ + struct { + uint64_t _unused_vbar; + uint64_t vbar_ns; + uint64_t hvbar; + uint64_t vbar_s; + }; + uint64_t vbar_el[4]; + }; uint64_t mvbar; /* (monitor) vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint64_t contextidr_el1; /* Context ID. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 2b0918f..8543813 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -918,9 +918,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .resetvalue = 0, .writefn = pmintenclr_write, }, { .name = "VBAR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .writefn = vbar_write, - .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), - .resetvalue = 0 }, + .access = PL1_RW, .writefn = vbar_write, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), + offsetof(CPUARMState, cp15.vbar_ns) } }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, @@ -2313,6 +2313,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, .type = ARM_CP_NO_MIGRATE, .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, + { .name = "VBAR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 0, + .access = PL1_RW, .writefn = vbar_write, + .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), + .resetvalue = 0 }, { .name = "CSSELR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, @@ -4451,7 +4456,7 @@ void arm_cpu_do_interrupt(CPUState *cs) * This register is only followed in non-monitor mode, and is banked. * Note: only bits 31:5 are valid. */ - addr += env->cp15.vbar_el[1]; + addr += A32_BANKED_CURRENT_REG_GET(env, vbar); } if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {