From patchwork Tue Sep 30 21:49:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 395355 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8BFFD1400E0 for ; Wed, 1 Oct 2014 08:13:01 +1000 (EST) Received: from localhost ([::1]:46833 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5fH-0002Iw-Lx for incoming@patchwork.ozlabs.org; Tue, 30 Sep 2014 18:12:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43544) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5Jy-0001DQ-B0 for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:51:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZ5Jp-00043a-PR for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:58 -0400 Received: from mail-pd0-f172.google.com ([209.85.192.172]:42862) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5Jo-00042v-DV for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:49 -0400 Received: by mail-pd0-f172.google.com with SMTP id p10so3624829pdj.3 for ; Tue, 30 Sep 2014 14:50:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BjPS07dba5qoOMwm7jtMWgalr152NhAivh81mvqSc6Q=; b=MsLkF2tuJoI6TzPRnaclYK6BjYNUSaeflyjBAnziCthkxXc6CkpztTTZQJytsXGdP+ XVMfqDJWFha84epWqnpiaPo4qdK4Ml0/sOd/PQuJ1sc34DcAylb8m5ZBZXrSEjP36NyW Ckmvtkvs68XNFcqUoNHJgxrZbrAIO9NTAr6AUSFtr0/6xmdI5vX+NaT0nInK3oIXJfJ+ b/shjnaYDgvOFRLW/TV49jZFZ8Vk7GhIdkcoSFsnubGebB43hEMf7nE0txYZ1JYKV1rm z1eE8sfxCIeoOl03xlfKjo/bZQJPcZuj6walCGCGKe5nsQkIk3EDcTRB/fQMFFQKbS8J gD4Q== X-Gm-Message-State: ALoCoQkBlXS6eh4NFcpsq9jYLQRPvaziO0QR29/t47TfTzUnX+DyzJeRpL6xgYO6n2BzPkZtX/46 X-Received: by 10.70.89.12 with SMTP id bk12mr44310278pdb.45.1412113832588; Tue, 30 Sep 2014 14:50:32 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id qy1sm16027662pbc.27.2014.09.30.14.50.31 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 30 Sep 2014 14:50:31 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 30 Sep 2014 16:49:37 -0500 Message-Id: <1412113785-21525-26-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.172 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v5 25/33] target-arm: make IFSR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) IFSR has a secure and a non-secure instance. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 9 +++++---- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 3661e85..5f9edc5 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -256,7 +256,15 @@ typedef struct CPUARMState { uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint64_t hcr_el2; /* Hypervisor configuration register */ uint64_t scr_el3; /* Secure configuration register. */ - uint32_t ifsr_el2; /* Fault status registers. */ + union { /* Fault status registers. */ + struct { + uint32_t ifsr_ns; + uint32_t ifsr_s; + }; + struct { + uint32_t ifsr32_el2; + }; + }; uint64_t esr_el[4]; uint32_t c6_region[8]; /* MPU base/size registers. */ uint64_t far_el[4]; /* Fault address registers. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index c2d44d2..a083566 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1666,8 +1666,9 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), .resetfn = arm_cp_reset_ignore, }, { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, - .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, }, + .access = PL1_RW, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifsr_s), + offsetof(CPUARMState, cp15.ifsr_ns) } }, { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, .access = PL1_RW, @@ -4377,11 +4378,11 @@ void arm_cpu_do_interrupt(CPUState *cs) env->exception.fsr = 2; /* Fall through to prefetch abort. */ case EXCP_PREFETCH_ABORT: - env->cp15.ifsr_el2 = env->exception.fsr; + A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32, env->exception.vaddress); qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", - env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress); + env->exception.fsr, (uint32_t)env->exception.vaddress); new_mode = ARM_CPU_MODE_ABT; addr = 0x0c; mask = CPSR_A | CPSR_I;