Message ID | 1407278474-17559-1-git-send-email-eblake@redhat.com |
---|---|
State | New |
Headers | show |
On 5 August 2014 23:41, Eric Blake <eblake@redhat.com> wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Reviewed-by: Greg Bellows <greg.bellows@linaro.org> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > Message-id: 1402994746-8328-7-git-send-email-edgar.iglesias@gmail.com > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Hi Eric; why are you retransmitting these target-arm patches? They don't seem to match up with your cover letter... thanks -- PMM
On 08/05/2014 05:08 PM, Peter Maydell wrote: > On 5 August 2014 23:41, Eric Blake <eblake@redhat.com> wrote: >> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> >> >> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> >> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> >> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> >> Message-id: 1402994746-8328-7-git-send-email-edgar.iglesias@gmail.com >> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > > Hi Eric; why are you retransmitting these target-arm patches? > They don't seem to match up with your cover letter... Shoot, 'git send-email' misbehaved on me after the first try died mid-send. Looks like 11-14 is bogus. I'll resend the correct series shortly :(
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 3d9cf57..79205ba 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -187,7 +187,7 @@ typedef struct CPUARMState { uint32_t ifsr_el2; /* Fault status registers. */ uint64_t esr_el[4]; uint32_t c6_region[8]; /* MPU base/size registers. */ - uint64_t far_el[2]; /* Fault address registers. */ + uint64_t far_el[4]; /* Fault address registers. */ uint64_t par_el1; /* Translation result. */ uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; diff --git a/target-arm/helper.c b/target-arm/helper.c index f4845b0..a7f82f3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2131,6 +2131,9 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, + { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, @@ -2153,6 +2156,9 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, + { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,