From patchwork Sun Aug 3 08:53:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Lackorzynski X-Patchwork-Id: 375997 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 03195140077 for ; Sun, 3 Aug 2014 18:54:38 +1000 (EST) Received: from localhost ([::1]:47264 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XDrYq-00030k-0H for incoming@patchwork.ozlabs.org; Sun, 03 Aug 2014 04:54:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48833) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XDrYK-00025Y-47 for qemu-devel@nongnu.org; Sun, 03 Aug 2014 04:54:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XDrY7-0007BR-E4 for qemu-devel@nongnu.org; Sun, 03 Aug 2014 04:54:04 -0400 Received: from os.inf.tu-dresden.de ([141.76.48.99]:37368) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XDrY7-0007Ax-82 for qemu-devel@nongnu.org; Sun, 03 Aug 2014 04:53:51 -0400 Received: from erwin.inf.tu-dresden.de ([141.76.48.80] helo=x) by os.inf.tu-dresden.de with esmtp (Exim 4.83) id 1XDrY4-000473-Qg for qemu-devel@nongnu.org; Sun, 03 Aug 2014 10:53:48 +0200 From: Adam Lackorzynski To: qemu-devel@nongnu.org Date: Sun, 3 Aug 2014 10:53:47 +0200 Message-Id: <1407056027-7522-4-git-send-email-adam@os.inf.tu-dresden.de> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1407056027-7522-1-git-send-email-adam@os.inf.tu-dresden.de> References: <1407056027-7522-1-git-send-email-adam@os.inf.tu-dresden.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 141.76.48.99 Subject: [Qemu-devel] [PATCH 3/3] arm_gic: GICD_ICFGR: Do not force edge-triggered PPIs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Using GICD_ICFGR for PPIs forces PPIs to edge-triggered mode, although they have been initialised to level-triggered. This affects all interrupts covered by the write access. Change the handling of PPIs to not force a specific mode. It is implementation defined whether setting the mode of PPIs is supported. Signed-off-by: Adam Lackorzynski --- hw/intc/arm_gic.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index cd6e6ea..066a7f2 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -558,8 +558,6 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; - if (irq < GIC_INTERNAL) - value |= 0xaa; for (i = 0; i < 4; i++) { if (value & (1 << (i * 2))) { GIC_SET_MODEL(irq + i);