From patchwork Fri Aug 1 05:27:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Beno=C3=AEt_Canet?= X-Patchwork-Id: 375557 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8F9C31400E9 for ; Fri, 1 Aug 2014 15:38:35 +1000 (EST) Received: from localhost ([::1]:59964 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XD5Y1-00081i-E7 for incoming@patchwork.ozlabs.org; Fri, 01 Aug 2014 01:38:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33705) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XD5OI-0007xh-L5 for qemu-devel@nongnu.org; Fri, 01 Aug 2014 01:28:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XD5O2-0003fG-RB for qemu-devel@nongnu.org; Fri, 01 Aug 2014 01:28:30 -0400 Received: from lputeaux-656-01-25-125.w80-12.abo.wanadoo.fr ([80.12.84.125]:59404 helo=paradis.irqsave.net) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XD5O1-0003c8-Rh for qemu-devel@nongnu.org; Fri, 01 Aug 2014 01:28:14 -0400 Received: from localhost.localdomain (laure.irqsave.net [192.168.77.2]) by paradis.irqsave.net (Postfix) with ESMTP id 843A0C3144; Fri, 1 Aug 2014 07:28:11 +0200 (CEST) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= To: qemu-devel@nongnu.org Date: Fri, 1 Aug 2014 07:27:13 +0200 Message-Id: <1406870842-17988-16-git-send-email-benoit.canet@irqsave.net> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1406870842-17988-1-git-send-email-benoit.canet@irqsave.net> References: <1406870842-17988-1-git-send-email-benoit.canet@irqsave.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 80.12.84.125 Cc: kwolf@redhat.com, =?UTF-8?q?Beno=C3=AEt=20Canet?= , Benoit Canet , mreitz@redhat.com, stefanha@redhat.com Subject: [Qemu-devel] [PATCH v1 15/24] monitor: Move mon_cmd_t arrays and some function from monitor.c to monitor-system.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Also add sizeof variables for mon_cmd_t arrays for cross modules usage. Signed-off-by: Benoit Canet --- monitor-system.c | 984 ++++++++++++++++++++++++++++++++++++++++++++++++++++ monitor.c | 1010 ++---------------------------------------------------- 2 files changed, 1007 insertions(+), 987 deletions(-) diff --git a/monitor-system.c b/monitor-system.c index 9e9a4ac..5b5f1ed 100644 --- a/monitor-system.c +++ b/monitor-system.c @@ -1411,3 +1411,987 @@ void do_loadvm(Monitor *mon, const QDict *qdict) vm_start(); } } + +/* Please update hmp-commands.hx when adding or changing commands */ +mon_cmd_t info_cmds[] = { + { + .name = "version", + .args_type = "", + .params = "", + .help = "show the version of QEMU", + .mhandler.cmd = hmp_info_version, + }, + { + .name = "network", + .args_type = "", + .params = "", + .help = "show the network state", + .mhandler.cmd = do_info_network, + }, + { + .name = "chardev", + .args_type = "", + .params = "", + .help = "show the character devices", + .mhandler.cmd = hmp_info_chardev, + }, + { + .name = "block", + .args_type = "verbose:-v,device:B?", + .params = "[-v] [device]", + .help = "show info of one block device or all block devices " + "(and details of images with -v option)", + .mhandler.cmd = hmp_info_block, + }, + { + .name = "blockstats", + .args_type = "", + .params = "", + .help = "show block device statistics", + .mhandler.cmd = hmp_info_blockstats, + }, + { + .name = "block-jobs", + .args_type = "", + .params = "", + .help = "show progress of ongoing block device operations", + .mhandler.cmd = hmp_info_block_jobs, + }, + { + .name = "registers", + .args_type = "", + .params = "", + .help = "show the cpu registers", + .mhandler.cmd = do_info_registers, + }, + { + .name = "cpus", + .args_type = "", + .params = "", + .help = "show infos for each CPU", + .mhandler.cmd = hmp_info_cpus, + }, + { + .name = "history", + .args_type = "", + .params = "", + .help = "show the command line history", + .mhandler.cmd = do_info_history, + }, +#if defined(TARGET_I386) || defined(TARGET_PPC) || defined(TARGET_MIPS) || \ + defined(TARGET_LM32) || (defined(TARGET_SPARC) && !defined(TARGET_SPARC64)) + { + .name = "irq", + .args_type = "", + .params = "", + .help = "show the interrupts statistics (if available)", +#ifdef TARGET_SPARC + .mhandler.cmd = sun4m_irq_info, +#elif defined(TARGET_LM32) + .mhandler.cmd = lm32_irq_info, +#else + .mhandler.cmd = irq_info, +#endif + }, + { + .name = "pic", + .args_type = "", + .params = "", + .help = "show i8259 (PIC) state", +#ifdef TARGET_SPARC + .mhandler.cmd = sun4m_pic_info, +#elif defined(TARGET_LM32) + .mhandler.cmd = lm32_do_pic_info, +#else + .mhandler.cmd = pic_info, +#endif + }, +#endif + { + .name = "pci", + .args_type = "", + .params = "", + .help = "show PCI info", + .mhandler.cmd = hmp_info_pci, + }, +#if defined(TARGET_I386) || defined(TARGET_SH4) || defined(TARGET_SPARC) || \ + defined(TARGET_PPC) || defined(TARGET_XTENSA) + { + .name = "tlb", + .args_type = "", + .params = "", + .help = "show virtual to physical memory mappings", + .mhandler.cmd = tlb_info, + }, +#endif +#if defined(TARGET_I386) + { + .name = "mem", + .args_type = "", + .params = "", + .help = "show the active virtual memory mappings", + .mhandler.cmd = mem_info, + }, +#endif + { + .name = "mtree", + .args_type = "", + .params = "", + .help = "show memory tree", + .mhandler.cmd = do_info_mtree, + }, + { + .name = "jit", + .args_type = "", + .params = "", + .help = "show dynamic compiler info", + .mhandler.cmd = do_info_jit, + }, + { + .name = "kvm", + .args_type = "", + .params = "", + .help = "show KVM information", + .mhandler.cmd = hmp_info_kvm, + }, + { + .name = "numa", + .args_type = "", + .params = "", + .help = "show NUMA information", + .mhandler.cmd = do_info_numa, + }, + { + .name = "usb", + .args_type = "", + .params = "", + .help = "show guest USB devices", + .mhandler.cmd = usb_info, + }, + { + .name = "usbhost", + .args_type = "", + .params = "", + .help = "show host USB devices", + .mhandler.cmd = usb_host_info, + }, + { + .name = "profile", + .args_type = "", + .params = "", + .help = "show profiling information", + .mhandler.cmd = do_info_profile, + }, + { + .name = "capture", + .args_type = "", + .params = "", + .help = "show capture information", + .mhandler.cmd = do_info_capture, + }, + { + .name = "snapshots", + .args_type = "", + .params = "", + .help = "show the currently saved VM snapshots", + .mhandler.cmd = do_info_snapshots, + }, + { + .name = "status", + .args_type = "", + .params = "", + .help = "show the current VM status (running|paused)", + .mhandler.cmd = hmp_info_status, + }, + { + .name = "pcmcia", + .args_type = "", + .params = "", + .help = "show guest PCMCIA status", + .mhandler.cmd = pcmcia_info, + }, + { + .name = "mice", + .args_type = "", + .params = "", + .help = "show which guest mouse is receiving events", + .mhandler.cmd = hmp_info_mice, + }, + { + .name = "vnc", + .args_type = "", + .params = "", + .help = "show the vnc server status", + .mhandler.cmd = hmp_info_vnc, + }, +#if defined(CONFIG_SPICE) + { + .name = "spice", + .args_type = "", + .params = "", + .help = "show the spice server status", + .mhandler.cmd = hmp_info_spice, + }, +#endif + { + .name = "name", + .args_type = "", + .params = "", + .help = "show the current VM name", + .mhandler.cmd = hmp_info_name, + }, + { + .name = "uuid", + .args_type = "", + .params = "", + .help = "show the current VM UUID", + .mhandler.cmd = hmp_info_uuid, + }, + { + .name = "cpustats", + .args_type = "", + .params = "", + .help = "show CPU statistics", + .mhandler.cmd = do_info_cpu_stats, + }, +#if defined(CONFIG_SLIRP) + { + .name = "usernet", + .args_type = "", + .params = "", + .help = "show user network stack connection states", + .mhandler.cmd = do_info_usernet, + }, +#endif + { + .name = "migrate", + .args_type = "", + .params = "", + .help = "show migration status", + .mhandler.cmd = hmp_info_migrate, + }, + { + .name = "migrate_capabilities", + .args_type = "", + .params = "", + .help = "show current migration capabilities", + .mhandler.cmd = hmp_info_migrate_capabilities, + }, + { + .name = "migrate_cache_size", + .args_type = "", + .params = "", + .help = "show current migration xbzrle cache size", + .mhandler.cmd = hmp_info_migrate_cache_size, + }, + { + .name = "balloon", + .args_type = "", + .params = "", + .help = "show balloon information", + .mhandler.cmd = hmp_info_balloon, + }, + { + .name = "qtree", + .args_type = "", + .params = "", + .help = "show device tree", + .mhandler.cmd = do_info_qtree, + }, + { + .name = "qdm", + .args_type = "", + .params = "", + .help = "show qdev device model list", + .mhandler.cmd = do_info_qdm, + }, + { + .name = "roms", + .args_type = "", + .params = "", + .help = "show roms", + .mhandler.cmd = do_info_roms, + }, + { + .name = "trace-events", + .args_type = "", + .params = "", + .help = "show available trace-events & their state", + .mhandler.cmd = do_trace_print_events, + }, + { + .name = "tpm", + .args_type = "", + .params = "", + .help = "show the TPM device", + .mhandler.cmd = hmp_info_tpm, + }, + { + .name = "memdev", + .args_type = "", + .params = "", + .help = "show memory backends", + .mhandler.cmd = hmp_info_memdev, + }, + { + .name = NULL, + }, +}; + +/* mon_cmds and info_cmds would be sorted at runtime */ +mon_cmd_t mon_cmds[] = { +#include "hmp-commands.h" + { NULL, NULL, }, +}; + +const mon_cmd_t qmp_cmds[] = { +#include "qmp-commands-old.h" + { /* NULL */ }, +}; + +/*******************************************************************/ + +static const char *pch; +static sigjmp_buf expr_env; + +#define MD_TLONG 0 +#define MD_I32 1 + +typedef struct MonitorDef { + const char *name; + int offset; + target_long (*get_value)(const struct MonitorDef *md, int val); + int type; +} MonitorDef; + +#if defined(TARGET_I386) +static target_long monitor_get_pc (const struct MonitorDef *md, int val) +{ + CPUArchState *env = mon_get_cpu(); + return env->eip + env->segs[R_CS].base; +} +#endif + +#if defined(TARGET_PPC) +static target_long monitor_get_ccr (const struct MonitorDef *md, int val) +{ + CPUArchState *env = mon_get_cpu(); + unsigned int u; + int i; + + u = 0; + for (i = 0; i < 8; i++) + u |= env->crf[i] << (32 - (4 * i)); + + return u; +} + +static target_long monitor_get_msr (const struct MonitorDef *md, int val) +{ + CPUArchState *env = mon_get_cpu(); + return env->msr; +} + +static target_long monitor_get_xer (const struct MonitorDef *md, int val) +{ + CPUArchState *env = mon_get_cpu(); + return env->xer; +} + +static target_long monitor_get_decr (const struct MonitorDef *md, int val) +{ + CPUArchState *env = mon_get_cpu(); + return cpu_ppc_load_decr(env); +} + +static target_long monitor_get_tbu (const struct MonitorDef *md, int val) +{ + CPUArchState *env = mon_get_cpu(); + return cpu_ppc_load_tbu(env); +} + +static target_long monitor_get_tbl (const struct MonitorDef *md, int val) +{ + CPUArchState *env = mon_get_cpu(); + return cpu_ppc_load_tbl(env); +} +#endif + +#if defined(TARGET_SPARC) +#ifndef TARGET_SPARC64 +static target_long monitor_get_psr (const struct MonitorDef *md, int val) +{ + CPUArchState *env = mon_get_cpu(); + + return cpu_get_psr(env); +} +#endif + +static target_long monitor_get_reg(const struct MonitorDef *md, int val) +{ + CPUArchState *env = mon_get_cpu(); + return env->regwptr[val]; +} +#endif + +static const MonitorDef monitor_defs[] = { +#ifdef TARGET_I386 + +#define SEG(name, seg) \ + { name, offsetof(CPUX86State, segs[seg].selector), NULL, MD_I32 },\ + { name ".base", offsetof(CPUX86State, segs[seg].base) },\ + { name ".limit", offsetof(CPUX86State, segs[seg].limit), NULL, MD_I32 }, + + { "eax", offsetof(CPUX86State, regs[0]) }, + { "ecx", offsetof(CPUX86State, regs[1]) }, + { "edx", offsetof(CPUX86State, regs[2]) }, + { "ebx", offsetof(CPUX86State, regs[3]) }, + { "esp|sp", offsetof(CPUX86State, regs[4]) }, + { "ebp|fp", offsetof(CPUX86State, regs[5]) }, + { "esi", offsetof(CPUX86State, regs[6]) }, + { "edi", offsetof(CPUX86State, regs[7]) }, +#ifdef TARGET_X86_64 + { "r8", offsetof(CPUX86State, regs[8]) }, + { "r9", offsetof(CPUX86State, regs[9]) }, + { "r10", offsetof(CPUX86State, regs[10]) }, + { "r11", offsetof(CPUX86State, regs[11]) }, + { "r12", offsetof(CPUX86State, regs[12]) }, + { "r13", offsetof(CPUX86State, regs[13]) }, + { "r14", offsetof(CPUX86State, regs[14]) }, + { "r15", offsetof(CPUX86State, regs[15]) }, +#endif + { "eflags", offsetof(CPUX86State, eflags) }, + { "eip", offsetof(CPUX86State, eip) }, + SEG("cs", R_CS) + SEG("ds", R_DS) + SEG("es", R_ES) + SEG("ss", R_SS) + SEG("fs", R_FS) + SEG("gs", R_GS) + { "pc", 0, monitor_get_pc, }, +#elif defined(TARGET_PPC) + /* General purpose registers */ + { "r0", offsetof(CPUPPCState, gpr[0]) }, + { "r1", offsetof(CPUPPCState, gpr[1]) }, + { "r2", offsetof(CPUPPCState, gpr[2]) }, + { "r3", offsetof(CPUPPCState, gpr[3]) }, + { "r4", offsetof(CPUPPCState, gpr[4]) }, + { "r5", offsetof(CPUPPCState, gpr[5]) }, + { "r6", offsetof(CPUPPCState, gpr[6]) }, + { "r7", offsetof(CPUPPCState, gpr[7]) }, + { "r8", offsetof(CPUPPCState, gpr[8]) }, + { "r9", offsetof(CPUPPCState, gpr[9]) }, + { "r10", offsetof(CPUPPCState, gpr[10]) }, + { "r11", offsetof(CPUPPCState, gpr[11]) }, + { "r12", offsetof(CPUPPCState, gpr[12]) }, + { "r13", offsetof(CPUPPCState, gpr[13]) }, + { "r14", offsetof(CPUPPCState, gpr[14]) }, + { "r15", offsetof(CPUPPCState, gpr[15]) }, + { "r16", offsetof(CPUPPCState, gpr[16]) }, + { "r17", offsetof(CPUPPCState, gpr[17]) }, + { "r18", offsetof(CPUPPCState, gpr[18]) }, + { "r19", offsetof(CPUPPCState, gpr[19]) }, + { "r20", offsetof(CPUPPCState, gpr[20]) }, + { "r21", offsetof(CPUPPCState, gpr[21]) }, + { "r22", offsetof(CPUPPCState, gpr[22]) }, + { "r23", offsetof(CPUPPCState, gpr[23]) }, + { "r24", offsetof(CPUPPCState, gpr[24]) }, + { "r25", offsetof(CPUPPCState, gpr[25]) }, + { "r26", offsetof(CPUPPCState, gpr[26]) }, + { "r27", offsetof(CPUPPCState, gpr[27]) }, + { "r28", offsetof(CPUPPCState, gpr[28]) }, + { "r29", offsetof(CPUPPCState, gpr[29]) }, + { "r30", offsetof(CPUPPCState, gpr[30]) }, + { "r31", offsetof(CPUPPCState, gpr[31]) }, + /* Floating point registers */ + { "f0", offsetof(CPUPPCState, fpr[0]) }, + { "f1", offsetof(CPUPPCState, fpr[1]) }, + { "f2", offsetof(CPUPPCState, fpr[2]) }, + { "f3", offsetof(CPUPPCState, fpr[3]) }, + { "f4", offsetof(CPUPPCState, fpr[4]) }, + { "f5", offsetof(CPUPPCState, fpr[5]) }, + { "f6", offsetof(CPUPPCState, fpr[6]) }, + { "f7", offsetof(CPUPPCState, fpr[7]) }, + { "f8", offsetof(CPUPPCState, fpr[8]) }, + { "f9", offsetof(CPUPPCState, fpr[9]) }, + { "f10", offsetof(CPUPPCState, fpr[10]) }, + { "f11", offsetof(CPUPPCState, fpr[11]) }, + { "f12", offsetof(CPUPPCState, fpr[12]) }, + { "f13", offsetof(CPUPPCState, fpr[13]) }, + { "f14", offsetof(CPUPPCState, fpr[14]) }, + { "f15", offsetof(CPUPPCState, fpr[15]) }, + { "f16", offsetof(CPUPPCState, fpr[16]) }, + { "f17", offsetof(CPUPPCState, fpr[17]) }, + { "f18", offsetof(CPUPPCState, fpr[18]) }, + { "f19", offsetof(CPUPPCState, fpr[19]) }, + { "f20", offsetof(CPUPPCState, fpr[20]) }, + { "f21", offsetof(CPUPPCState, fpr[21]) }, + { "f22", offsetof(CPUPPCState, fpr[22]) }, + { "f23", offsetof(CPUPPCState, fpr[23]) }, + { "f24", offsetof(CPUPPCState, fpr[24]) }, + { "f25", offsetof(CPUPPCState, fpr[25]) }, + { "f26", offsetof(CPUPPCState, fpr[26]) }, + { "f27", offsetof(CPUPPCState, fpr[27]) }, + { "f28", offsetof(CPUPPCState, fpr[28]) }, + { "f29", offsetof(CPUPPCState, fpr[29]) }, + { "f30", offsetof(CPUPPCState, fpr[30]) }, + { "f31", offsetof(CPUPPCState, fpr[31]) }, + { "fpscr", offsetof(CPUPPCState, fpscr) }, + /* Next instruction pointer */ + { "nip|pc", offsetof(CPUPPCState, nip) }, + { "lr", offsetof(CPUPPCState, lr) }, + { "ctr", offsetof(CPUPPCState, ctr) }, + { "decr", 0, &monitor_get_decr, }, + { "ccr", 0, &monitor_get_ccr, }, + /* Machine state register */ + { "msr", 0, &monitor_get_msr, }, + { "xer", 0, &monitor_get_xer, }, + { "tbu", 0, &monitor_get_tbu, }, + { "tbl", 0, &monitor_get_tbl, }, + /* Segment registers */ + { "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) }, + { "sr0", offsetof(CPUPPCState, sr[0]) }, + { "sr1", offsetof(CPUPPCState, sr[1]) }, + { "sr2", offsetof(CPUPPCState, sr[2]) }, + { "sr3", offsetof(CPUPPCState, sr[3]) }, + { "sr4", offsetof(CPUPPCState, sr[4]) }, + { "sr5", offsetof(CPUPPCState, sr[5]) }, + { "sr6", offsetof(CPUPPCState, sr[6]) }, + { "sr7", offsetof(CPUPPCState, sr[7]) }, + { "sr8", offsetof(CPUPPCState, sr[8]) }, + { "sr9", offsetof(CPUPPCState, sr[9]) }, + { "sr10", offsetof(CPUPPCState, sr[10]) }, + { "sr11", offsetof(CPUPPCState, sr[11]) }, + { "sr12", offsetof(CPUPPCState, sr[12]) }, + { "sr13", offsetof(CPUPPCState, sr[13]) }, + { "sr14", offsetof(CPUPPCState, sr[14]) }, + { "sr15", offsetof(CPUPPCState, sr[15]) }, + /* Too lazy to put BATs... */ + { "pvr", offsetof(CPUPPCState, spr[SPR_PVR]) }, + + { "srr0", offsetof(CPUPPCState, spr[SPR_SRR0]) }, + { "srr1", offsetof(CPUPPCState, spr[SPR_SRR1]) }, + { "dar", offsetof(CPUPPCState, spr[SPR_DAR]) }, + { "dsisr", offsetof(CPUPPCState, spr[SPR_DSISR]) }, + { "cfar", offsetof(CPUPPCState, spr[SPR_CFAR]) }, + { "sprg0", offsetof(CPUPPCState, spr[SPR_SPRG0]) }, + { "sprg1", offsetof(CPUPPCState, spr[SPR_SPRG1]) }, + { "sprg2", offsetof(CPUPPCState, spr[SPR_SPRG2]) }, + { "sprg3", offsetof(CPUPPCState, spr[SPR_SPRG3]) }, + { "sprg4", offsetof(CPUPPCState, spr[SPR_SPRG4]) }, + { "sprg5", offsetof(CPUPPCState, spr[SPR_SPRG5]) }, + { "sprg6", offsetof(CPUPPCState, spr[SPR_SPRG6]) }, + { "sprg7", offsetof(CPUPPCState, spr[SPR_SPRG7]) }, + { "pid", offsetof(CPUPPCState, spr[SPR_BOOKE_PID]) }, + { "csrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR0]) }, + { "csrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR1]) }, + { "esr", offsetof(CPUPPCState, spr[SPR_BOOKE_ESR]) }, + { "dear", offsetof(CPUPPCState, spr[SPR_BOOKE_DEAR]) }, + { "mcsr", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSR]) }, + { "tsr", offsetof(CPUPPCState, spr[SPR_BOOKE_TSR]) }, + { "tcr", offsetof(CPUPPCState, spr[SPR_BOOKE_TCR]) }, + { "vrsave", offsetof(CPUPPCState, spr[SPR_VRSAVE]) }, + { "pir", offsetof(CPUPPCState, spr[SPR_BOOKE_PIR]) }, + { "mcsrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR0]) }, + { "mcsrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR1]) }, + { "decar", offsetof(CPUPPCState, spr[SPR_BOOKE_DECAR]) }, + { "ivpr", offsetof(CPUPPCState, spr[SPR_BOOKE_IVPR]) }, + { "epcr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPCR]) }, + { "sprg8", offsetof(CPUPPCState, spr[SPR_BOOKE_SPRG8]) }, + { "ivor0", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR0]) }, + { "ivor1", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR1]) }, + { "ivor2", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR2]) }, + { "ivor3", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR3]) }, + { "ivor4", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR4]) }, + { "ivor5", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR5]) }, + { "ivor6", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR6]) }, + { "ivor7", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR7]) }, + { "ivor8", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR8]) }, + { "ivor9", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR9]) }, + { "ivor10", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR10]) }, + { "ivor11", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR11]) }, + { "ivor12", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR12]) }, + { "ivor13", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR13]) }, + { "ivor14", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR14]) }, + { "ivor15", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR15]) }, + { "ivor32", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR32]) }, + { "ivor33", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR33]) }, + { "ivor34", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR34]) }, + { "ivor35", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR35]) }, + { "ivor36", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR36]) }, + { "ivor37", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR37]) }, + { "mas0", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS0]) }, + { "mas1", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS1]) }, + { "mas2", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS2]) }, + { "mas3", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS3]) }, + { "mas4", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS4]) }, + { "mas6", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS6]) }, + { "mas7", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS7]) }, + { "mmucfg", offsetof(CPUPPCState, spr[SPR_MMUCFG]) }, + { "tlb0cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB0CFG]) }, + { "tlb1cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB1CFG]) }, + { "epr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPR]) }, + { "eplc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPLC]) }, + { "epsc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPSC]) }, + { "svr", offsetof(CPUPPCState, spr[SPR_E500_SVR]) }, + { "mcar", offsetof(CPUPPCState, spr[SPR_Exxx_MCAR]) }, + { "pid1", offsetof(CPUPPCState, spr[SPR_BOOKE_PID1]) }, + { "pid2", offsetof(CPUPPCState, spr[SPR_BOOKE_PID2]) }, + { "hid0", offsetof(CPUPPCState, spr[SPR_HID0]) }, + +#elif defined(TARGET_SPARC) + { "g0", offsetof(CPUSPARCState, gregs[0]) }, + { "g1", offsetof(CPUSPARCState, gregs[1]) }, + { "g2", offsetof(CPUSPARCState, gregs[2]) }, + { "g3", offsetof(CPUSPARCState, gregs[3]) }, + { "g4", offsetof(CPUSPARCState, gregs[4]) }, + { "g5", offsetof(CPUSPARCState, gregs[5]) }, + { "g6", offsetof(CPUSPARCState, gregs[6]) }, + { "g7", offsetof(CPUSPARCState, gregs[7]) }, + { "o0", 0, monitor_get_reg }, + { "o1", 1, monitor_get_reg }, + { "o2", 2, monitor_get_reg }, + { "o3", 3, monitor_get_reg }, + { "o4", 4, monitor_get_reg }, + { "o5", 5, monitor_get_reg }, + { "o6", 6, monitor_get_reg }, + { "o7", 7, monitor_get_reg }, + { "l0", 8, monitor_get_reg }, + { "l1", 9, monitor_get_reg }, + { "l2", 10, monitor_get_reg }, + { "l3", 11, monitor_get_reg }, + { "l4", 12, monitor_get_reg }, + { "l5", 13, monitor_get_reg }, + { "l6", 14, monitor_get_reg }, + { "l7", 15, monitor_get_reg }, + { "i0", 16, monitor_get_reg }, + { "i1", 17, monitor_get_reg }, + { "i2", 18, monitor_get_reg }, + { "i3", 19, monitor_get_reg }, + { "i4", 20, monitor_get_reg }, + { "i5", 21, monitor_get_reg }, + { "i6", 22, monitor_get_reg }, + { "i7", 23, monitor_get_reg }, + { "pc", offsetof(CPUSPARCState, pc) }, + { "npc", offsetof(CPUSPARCState, npc) }, + { "y", offsetof(CPUSPARCState, y) }, +#ifndef TARGET_SPARC64 + { "psr", 0, &monitor_get_psr, }, + { "wim", offsetof(CPUSPARCState, wim) }, +#endif + { "tbr", offsetof(CPUSPARCState, tbr) }, + { "fsr", offsetof(CPUSPARCState, fsr) }, + { "f0", offsetof(CPUSPARCState, fpr[0].l.upper) }, + { "f1", offsetof(CPUSPARCState, fpr[0].l.lower) }, + { "f2", offsetof(CPUSPARCState, fpr[1].l.upper) }, + { "f3", offsetof(CPUSPARCState, fpr[1].l.lower) }, + { "f4", offsetof(CPUSPARCState, fpr[2].l.upper) }, + { "f5", offsetof(CPUSPARCState, fpr[2].l.lower) }, + { "f6", offsetof(CPUSPARCState, fpr[3].l.upper) }, + { "f7", offsetof(CPUSPARCState, fpr[3].l.lower) }, + { "f8", offsetof(CPUSPARCState, fpr[4].l.upper) }, + { "f9", offsetof(CPUSPARCState, fpr[4].l.lower) }, + { "f10", offsetof(CPUSPARCState, fpr[5].l.upper) }, + { "f11", offsetof(CPUSPARCState, fpr[5].l.lower) }, + { "f12", offsetof(CPUSPARCState, fpr[6].l.upper) }, + { "f13", offsetof(CPUSPARCState, fpr[6].l.lower) }, + { "f14", offsetof(CPUSPARCState, fpr[7].l.upper) }, + { "f15", offsetof(CPUSPARCState, fpr[7].l.lower) }, + { "f16", offsetof(CPUSPARCState, fpr[8].l.upper) }, + { "f17", offsetof(CPUSPARCState, fpr[8].l.lower) }, + { "f18", offsetof(CPUSPARCState, fpr[9].l.upper) }, + { "f19", offsetof(CPUSPARCState, fpr[9].l.lower) }, + { "f20", offsetof(CPUSPARCState, fpr[10].l.upper) }, + { "f21", offsetof(CPUSPARCState, fpr[10].l.lower) }, + { "f22", offsetof(CPUSPARCState, fpr[11].l.upper) }, + { "f23", offsetof(CPUSPARCState, fpr[11].l.lower) }, + { "f24", offsetof(CPUSPARCState, fpr[12].l.upper) }, + { "f25", offsetof(CPUSPARCState, fpr[12].l.lower) }, + { "f26", offsetof(CPUSPARCState, fpr[13].l.upper) }, + { "f27", offsetof(CPUSPARCState, fpr[13].l.lower) }, + { "f28", offsetof(CPUSPARCState, fpr[14].l.upper) }, + { "f29", offsetof(CPUSPARCState, fpr[14].l.lower) }, + { "f30", offsetof(CPUSPARCState, fpr[15].l.upper) }, + { "f31", offsetof(CPUSPARCState, fpr[15].l.lower) }, +#ifdef TARGET_SPARC64 + { "f32", offsetof(CPUSPARCState, fpr[16]) }, + { "f34", offsetof(CPUSPARCState, fpr[17]) }, + { "f36", offsetof(CPUSPARCState, fpr[18]) }, + { "f38", offsetof(CPUSPARCState, fpr[19]) }, + { "f40", offsetof(CPUSPARCState, fpr[20]) }, + { "f42", offsetof(CPUSPARCState, fpr[21]) }, + { "f44", offsetof(CPUSPARCState, fpr[22]) }, + { "f46", offsetof(CPUSPARCState, fpr[23]) }, + { "f48", offsetof(CPUSPARCState, fpr[24]) }, + { "f50", offsetof(CPUSPARCState, fpr[25]) }, + { "f52", offsetof(CPUSPARCState, fpr[26]) }, + { "f54", offsetof(CPUSPARCState, fpr[27]) }, + { "f56", offsetof(CPUSPARCState, fpr[28]) }, + { "f58", offsetof(CPUSPARCState, fpr[29]) }, + { "f60", offsetof(CPUSPARCState, fpr[30]) }, + { "f62", offsetof(CPUSPARCState, fpr[31]) }, + { "asi", offsetof(CPUSPARCState, asi) }, + { "pstate", offsetof(CPUSPARCState, pstate) }, + { "cansave", offsetof(CPUSPARCState, cansave) }, + { "canrestore", offsetof(CPUSPARCState, canrestore) }, + { "otherwin", offsetof(CPUSPARCState, otherwin) }, + { "wstate", offsetof(CPUSPARCState, wstate) }, + { "cleanwin", offsetof(CPUSPARCState, cleanwin) }, + { "fprs", offsetof(CPUSPARCState, fprs) }, +#endif +#endif + { NULL }, +}; + +static void GCC_FMT_ATTR(2, 3) QEMU_NORETURN +expr_error(Monitor *mon, const char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + monitor_vprintf(mon, fmt, ap); + monitor_printf(mon, "\n"); + va_end(ap); + siglongjmp(expr_env, 1); +} + +/* return 0 if OK, -1 if not found */ +static int get_monitor_def(target_long *pval, const char *name) +{ + const MonitorDef *md; + void *ptr; + + for(md = monitor_defs; md->name != NULL; md++) { + if (compare_cmd(name, md->name)) { + if (md->get_value) { + *pval = md->get_value(md, md->offset); + } else { + CPUArchState *env = mon_get_cpu(); + ptr = (uint8_t *)env + md->offset; + switch(md->type) { + case MD_I32: + *pval = *(int32_t *)ptr; + break; + case MD_TLONG: + *pval = *(target_long *)ptr; + break; + default: + *pval = 0; + break; + } + } + return 0; + } + } + return -1; +} + +static void next(void) +{ + if (*pch != '\0') { + pch++; + while (qemu_isspace(*pch)) + pch++; + } +} + +static int64_t expr_sum(Monitor *mon); + +static int64_t expr_unary(Monitor *mon) +{ + int64_t n; + char *p; + int ret; + + switch(*pch) { + case '+': + next(); + n = expr_unary(mon); + break; + case '-': + next(); + n = -expr_unary(mon); + break; + case '~': + next(); + n = ~expr_unary(mon); + break; + case '(': + next(); + n = expr_sum(mon); + if (*pch != ')') { + expr_error(mon, "')' expected"); + } + next(); + break; + case '\'': + pch++; + if (*pch == '\0') + expr_error(mon, "character constant expected"); + n = *pch; + pch++; + if (*pch != '\'') + expr_error(mon, "missing terminating \' character"); + next(); + break; + case '$': + { + char buf[128], *q; + target_long reg=0; + + pch++; + q = buf; + while ((*pch >= 'a' && *pch <= 'z') || + (*pch >= 'A' && *pch <= 'Z') || + (*pch >= '0' && *pch <= '9') || + *pch == '_' || *pch == '.') { + if ((q - buf) < sizeof(buf) - 1) + *q++ = *pch; + pch++; + } + while (qemu_isspace(*pch)) + pch++; + *q = 0; + ret = get_monitor_def(®, buf); + if (ret < 0) + expr_error(mon, "unknown register"); + n = reg; + } + break; + case '\0': + expr_error(mon, "unexpected end of expression"); + n = 0; + break; + default: + errno = 0; + n = strtoull(pch, &p, 0); + if (errno == ERANGE) { + expr_error(mon, "number too large"); + } + if (pch == p) { + expr_error(mon, "invalid char '%c' in expression", *p); + } + pch = p; + while (qemu_isspace(*pch)) + pch++; + break; + } + return n; +} + + +static int64_t expr_prod(Monitor *mon) +{ + int64_t val, val2; + int op; + + val = expr_unary(mon); + for(;;) { + op = *pch; + if (op != '*' && op != '/' && op != '%') + break; + next(); + val2 = expr_unary(mon); + switch(op) { + default: + case '*': + val *= val2; + break; + case '/': + case '%': + if (val2 == 0) + expr_error(mon, "division by zero"); + if (op == '/') + val /= val2; + else + val %= val2; + break; + } + } + return val; +} + +static int64_t expr_logic(Monitor *mon) +{ + int64_t val, val2; + int op; + + val = expr_prod(mon); + for(;;) { + op = *pch; + if (op != '&' && op != '|' && op != '^') + break; + next(); + val2 = expr_prod(mon); + switch(op) { + default: + case '&': + val &= val2; + break; + case '|': + val |= val2; + break; + case '^': + val ^= val2; + break; + } + } + return val; +} + +static int64_t expr_sum(Monitor *mon) +{ + int64_t val, val2; + int op; + + val = expr_logic(mon); + for(;;) { + op = *pch; + if (op != '+' && op != '-') + break; + next(); + val2 = expr_logic(mon); + if (op == '+') + val += val2; + else + val -= val2; + } + return val; +} + +int get_expr(Monitor *mon, int64_t *pval, const char **pp) +{ + pch = *pp; + if (sigsetjmp(expr_env, 0)) { + *pp = pch; + return -1; + } + while (qemu_isspace(*pch)) + pch++; + *pval = expr_sum(mon); + *pp = pch; + return 0; +} + +int get_double(Monitor *mon, double *pval, const char **pp) +{ + const char *p = *pp; + char *tailp; + double d; + + d = strtod(p, &tailp); + if (tailp == p) { + monitor_printf(mon, "Number expected\n"); + return -1; + } + if (d != d || d - d != 0) { + /* NaN or infinity */ + monitor_printf(mon, "Bad number\n"); + return -1; + } + *pval = d; + *pp = tailp; + return 0; +} + +size_t sizeof_mon_cmds = sizeof(mon_cmds); +size_t sizeof_info_cmds = sizeof(info_cmds); diff --git a/monitor.c b/monitor.c index 560d5e4..419da13 100644 --- a/monitor.c +++ b/monitor.c @@ -173,10 +173,27 @@ static QLIST_HEAD(mon_list, Monitor) mon_list; static QLIST_HEAD(mon_fdsets, MonFdset) mon_fdsets; static int mon_refcount; -mon_cmd_t mon_cmds[]; -mon_cmd_t info_cmds[]; - -const mon_cmd_t qmp_cmds[]; +#ifdef BLOCK_COMMAND_MONITOR +static mon_cmd_t mon_cmds[] = { + { NULL, NULL, }, +}; +size_t sizeof_mon_cmds = sizeof(mon_cmds); +static mon_cmd_t info_cmds[] = { + { + .name = NULL, + }, +}; +size_t sizeof_info_cmds = sizeof(info_cmds); +static const mon_cmd_t qmp_cmds[] = { + { /* NULL */ }, +}; +#else +extern mon_cmd_t mon_cmds[]; +extern size_t sizeof_mon_cmds; +extern mon_cmd_t info_cmds[]; +extern size_t sizeof_info_cmds; +extern const mon_cmd_t qmp_cmds[]; +#endif Monitor *cur_mon; Monitor *default_mon; @@ -1187,987 +1204,6 @@ int monitor_handle_fd_param2(Monitor *mon, const char *fdname, Error **errp) return fd; } -/* Please update hmp-commands.hx when adding or changing commands */ -mon_cmd_t info_cmds[] = { - { - .name = "version", - .args_type = "", - .params = "", - .help = "show the version of QEMU", - .mhandler.cmd = hmp_info_version, - }, - { - .name = "network", - .args_type = "", - .params = "", - .help = "show the network state", - .mhandler.cmd = do_info_network, - }, - { - .name = "chardev", - .args_type = "", - .params = "", - .help = "show the character devices", - .mhandler.cmd = hmp_info_chardev, - }, - { - .name = "block", - .args_type = "verbose:-v,device:B?", - .params = "[-v] [device]", - .help = "show info of one block device or all block devices " - "(and details of images with -v option)", - .mhandler.cmd = hmp_info_block, - }, - { - .name = "blockstats", - .args_type = "", - .params = "", - .help = "show block device statistics", - .mhandler.cmd = hmp_info_blockstats, - }, - { - .name = "block-jobs", - .args_type = "", - .params = "", - .help = "show progress of ongoing block device operations", - .mhandler.cmd = hmp_info_block_jobs, - }, - { - .name = "registers", - .args_type = "", - .params = "", - .help = "show the cpu registers", - .mhandler.cmd = do_info_registers, - }, - { - .name = "cpus", - .args_type = "", - .params = "", - .help = "show infos for each CPU", - .mhandler.cmd = hmp_info_cpus, - }, - { - .name = "history", - .args_type = "", - .params = "", - .help = "show the command line history", - .mhandler.cmd = do_info_history, - }, -#if defined(TARGET_I386) || defined(TARGET_PPC) || defined(TARGET_MIPS) || \ - defined(TARGET_LM32) || (defined(TARGET_SPARC) && !defined(TARGET_SPARC64)) - { - .name = "irq", - .args_type = "", - .params = "", - .help = "show the interrupts statistics (if available)", -#ifdef TARGET_SPARC - .mhandler.cmd = sun4m_irq_info, -#elif defined(TARGET_LM32) - .mhandler.cmd = lm32_irq_info, -#else - .mhandler.cmd = irq_info, -#endif - }, - { - .name = "pic", - .args_type = "", - .params = "", - .help = "show i8259 (PIC) state", -#ifdef TARGET_SPARC - .mhandler.cmd = sun4m_pic_info, -#elif defined(TARGET_LM32) - .mhandler.cmd = lm32_do_pic_info, -#else - .mhandler.cmd = pic_info, -#endif - }, -#endif - { - .name = "pci", - .args_type = "", - .params = "", - .help = "show PCI info", - .mhandler.cmd = hmp_info_pci, - }, -#if defined(TARGET_I386) || defined(TARGET_SH4) || defined(TARGET_SPARC) || \ - defined(TARGET_PPC) || defined(TARGET_XTENSA) - { - .name = "tlb", - .args_type = "", - .params = "", - .help = "show virtual to physical memory mappings", - .mhandler.cmd = tlb_info, - }, -#endif -#if defined(TARGET_I386) - { - .name = "mem", - .args_type = "", - .params = "", - .help = "show the active virtual memory mappings", - .mhandler.cmd = mem_info, - }, -#endif - { - .name = "mtree", - .args_type = "", - .params = "", - .help = "show memory tree", - .mhandler.cmd = do_info_mtree, - }, - { - .name = "jit", - .args_type = "", - .params = "", - .help = "show dynamic compiler info", - .mhandler.cmd = do_info_jit, - }, - { - .name = "kvm", - .args_type = "", - .params = "", - .help = "show KVM information", - .mhandler.cmd = hmp_info_kvm, - }, - { - .name = "numa", - .args_type = "", - .params = "", - .help = "show NUMA information", - .mhandler.cmd = do_info_numa, - }, - { - .name = "usb", - .args_type = "", - .params = "", - .help = "show guest USB devices", - .mhandler.cmd = usb_info, - }, - { - .name = "usbhost", - .args_type = "", - .params = "", - .help = "show host USB devices", - .mhandler.cmd = usb_host_info, - }, - { - .name = "profile", - .args_type = "", - .params = "", - .help = "show profiling information", - .mhandler.cmd = do_info_profile, - }, - { - .name = "capture", - .args_type = "", - .params = "", - .help = "show capture information", - .mhandler.cmd = do_info_capture, - }, - { - .name = "snapshots", - .args_type = "", - .params = "", - .help = "show the currently saved VM snapshots", - .mhandler.cmd = do_info_snapshots, - }, - { - .name = "status", - .args_type = "", - .params = "", - .help = "show the current VM status (running|paused)", - .mhandler.cmd = hmp_info_status, - }, - { - .name = "pcmcia", - .args_type = "", - .params = "", - .help = "show guest PCMCIA status", - .mhandler.cmd = pcmcia_info, - }, - { - .name = "mice", - .args_type = "", - .params = "", - .help = "show which guest mouse is receiving events", - .mhandler.cmd = hmp_info_mice, - }, - { - .name = "vnc", - .args_type = "", - .params = "", - .help = "show the vnc server status", - .mhandler.cmd = hmp_info_vnc, - }, -#if defined(CONFIG_SPICE) - { - .name = "spice", - .args_type = "", - .params = "", - .help = "show the spice server status", - .mhandler.cmd = hmp_info_spice, - }, -#endif - { - .name = "name", - .args_type = "", - .params = "", - .help = "show the current VM name", - .mhandler.cmd = hmp_info_name, - }, - { - .name = "uuid", - .args_type = "", - .params = "", - .help = "show the current VM UUID", - .mhandler.cmd = hmp_info_uuid, - }, - { - .name = "cpustats", - .args_type = "", - .params = "", - .help = "show CPU statistics", - .mhandler.cmd = do_info_cpu_stats, - }, -#if defined(CONFIG_SLIRP) - { - .name = "usernet", - .args_type = "", - .params = "", - .help = "show user network stack connection states", - .mhandler.cmd = do_info_usernet, - }, -#endif - { - .name = "migrate", - .args_type = "", - .params = "", - .help = "show migration status", - .mhandler.cmd = hmp_info_migrate, - }, - { - .name = "migrate_capabilities", - .args_type = "", - .params = "", - .help = "show current migration capabilities", - .mhandler.cmd = hmp_info_migrate_capabilities, - }, - { - .name = "migrate_cache_size", - .args_type = "", - .params = "", - .help = "show current migration xbzrle cache size", - .mhandler.cmd = hmp_info_migrate_cache_size, - }, - { - .name = "balloon", - .args_type = "", - .params = "", - .help = "show balloon information", - .mhandler.cmd = hmp_info_balloon, - }, - { - .name = "qtree", - .args_type = "", - .params = "", - .help = "show device tree", - .mhandler.cmd = do_info_qtree, - }, - { - .name = "qdm", - .args_type = "", - .params = "", - .help = "show qdev device model list", - .mhandler.cmd = do_info_qdm, - }, - { - .name = "roms", - .args_type = "", - .params = "", - .help = "show roms", - .mhandler.cmd = do_info_roms, - }, - { - .name = "trace-events", - .args_type = "", - .params = "", - .help = "show available trace-events & their state", - .mhandler.cmd = do_trace_print_events, - }, - { - .name = "tpm", - .args_type = "", - .params = "", - .help = "show the TPM device", - .mhandler.cmd = hmp_info_tpm, - }, - { - .name = "memdev", - .args_type = "", - .params = "", - .help = "show memory backends", - .mhandler.cmd = hmp_info_memdev, - }, - { - .name = NULL, - }, -}; - -/* mon_cmds and info_cmds would be sorted at runtime */ -mon_cmd_t mon_cmds[] = { -#include "hmp-commands.h" - { NULL, NULL, }, -}; - -const mon_cmd_t qmp_cmds[] = { -#include "qmp-commands-old.h" - { /* NULL */ }, -}; - -/*******************************************************************/ - -static const char *pch; -static sigjmp_buf expr_env; - -#define MD_TLONG 0 -#define MD_I32 1 - -typedef struct MonitorDef { - const char *name; - int offset; - target_long (*get_value)(const struct MonitorDef *md, int val); - int type; -} MonitorDef; - -#if defined(TARGET_I386) -static target_long monitor_get_pc (const struct MonitorDef *md, int val) -{ - CPUArchState *env = mon_get_cpu(); - return env->eip + env->segs[R_CS].base; -} -#endif - -#if defined(TARGET_PPC) -static target_long monitor_get_ccr (const struct MonitorDef *md, int val) -{ - CPUArchState *env = mon_get_cpu(); - unsigned int u; - int i; - - u = 0; - for (i = 0; i < 8; i++) - u |= env->crf[i] << (32 - (4 * i)); - - return u; -} - -static target_long monitor_get_msr (const struct MonitorDef *md, int val) -{ - CPUArchState *env = mon_get_cpu(); - return env->msr; -} - -static target_long monitor_get_xer (const struct MonitorDef *md, int val) -{ - CPUArchState *env = mon_get_cpu(); - return env->xer; -} - -static target_long monitor_get_decr (const struct MonitorDef *md, int val) -{ - CPUArchState *env = mon_get_cpu(); - return cpu_ppc_load_decr(env); -} - -static target_long monitor_get_tbu (const struct MonitorDef *md, int val) -{ - CPUArchState *env = mon_get_cpu(); - return cpu_ppc_load_tbu(env); -} - -static target_long monitor_get_tbl (const struct MonitorDef *md, int val) -{ - CPUArchState *env = mon_get_cpu(); - return cpu_ppc_load_tbl(env); -} -#endif - -#if defined(TARGET_SPARC) -#ifndef TARGET_SPARC64 -static target_long monitor_get_psr (const struct MonitorDef *md, int val) -{ - CPUArchState *env = mon_get_cpu(); - - return cpu_get_psr(env); -} -#endif - -static target_long monitor_get_reg(const struct MonitorDef *md, int val) -{ - CPUArchState *env = mon_get_cpu(); - return env->regwptr[val]; -} -#endif - -static const MonitorDef monitor_defs[] = { -#ifdef TARGET_I386 - -#define SEG(name, seg) \ - { name, offsetof(CPUX86State, segs[seg].selector), NULL, MD_I32 },\ - { name ".base", offsetof(CPUX86State, segs[seg].base) },\ - { name ".limit", offsetof(CPUX86State, segs[seg].limit), NULL, MD_I32 }, - - { "eax", offsetof(CPUX86State, regs[0]) }, - { "ecx", offsetof(CPUX86State, regs[1]) }, - { "edx", offsetof(CPUX86State, regs[2]) }, - { "ebx", offsetof(CPUX86State, regs[3]) }, - { "esp|sp", offsetof(CPUX86State, regs[4]) }, - { "ebp|fp", offsetof(CPUX86State, regs[5]) }, - { "esi", offsetof(CPUX86State, regs[6]) }, - { "edi", offsetof(CPUX86State, regs[7]) }, -#ifdef TARGET_X86_64 - { "r8", offsetof(CPUX86State, regs[8]) }, - { "r9", offsetof(CPUX86State, regs[9]) }, - { "r10", offsetof(CPUX86State, regs[10]) }, - { "r11", offsetof(CPUX86State, regs[11]) }, - { "r12", offsetof(CPUX86State, regs[12]) }, - { "r13", offsetof(CPUX86State, regs[13]) }, - { "r14", offsetof(CPUX86State, regs[14]) }, - { "r15", offsetof(CPUX86State, regs[15]) }, -#endif - { "eflags", offsetof(CPUX86State, eflags) }, - { "eip", offsetof(CPUX86State, eip) }, - SEG("cs", R_CS) - SEG("ds", R_DS) - SEG("es", R_ES) - SEG("ss", R_SS) - SEG("fs", R_FS) - SEG("gs", R_GS) - { "pc", 0, monitor_get_pc, }, -#elif defined(TARGET_PPC) - /* General purpose registers */ - { "r0", offsetof(CPUPPCState, gpr[0]) }, - { "r1", offsetof(CPUPPCState, gpr[1]) }, - { "r2", offsetof(CPUPPCState, gpr[2]) }, - { "r3", offsetof(CPUPPCState, gpr[3]) }, - { "r4", offsetof(CPUPPCState, gpr[4]) }, - { "r5", offsetof(CPUPPCState, gpr[5]) }, - { "r6", offsetof(CPUPPCState, gpr[6]) }, - { "r7", offsetof(CPUPPCState, gpr[7]) }, - { "r8", offsetof(CPUPPCState, gpr[8]) }, - { "r9", offsetof(CPUPPCState, gpr[9]) }, - { "r10", offsetof(CPUPPCState, gpr[10]) }, - { "r11", offsetof(CPUPPCState, gpr[11]) }, - { "r12", offsetof(CPUPPCState, gpr[12]) }, - { "r13", offsetof(CPUPPCState, gpr[13]) }, - { "r14", offsetof(CPUPPCState, gpr[14]) }, - { "r15", offsetof(CPUPPCState, gpr[15]) }, - { "r16", offsetof(CPUPPCState, gpr[16]) }, - { "r17", offsetof(CPUPPCState, gpr[17]) }, - { "r18", offsetof(CPUPPCState, gpr[18]) }, - { "r19", offsetof(CPUPPCState, gpr[19]) }, - { "r20", offsetof(CPUPPCState, gpr[20]) }, - { "r21", offsetof(CPUPPCState, gpr[21]) }, - { "r22", offsetof(CPUPPCState, gpr[22]) }, - { "r23", offsetof(CPUPPCState, gpr[23]) }, - { "r24", offsetof(CPUPPCState, gpr[24]) }, - { "r25", offsetof(CPUPPCState, gpr[25]) }, - { "r26", offsetof(CPUPPCState, gpr[26]) }, - { "r27", offsetof(CPUPPCState, gpr[27]) }, - { "r28", offsetof(CPUPPCState, gpr[28]) }, - { "r29", offsetof(CPUPPCState, gpr[29]) }, - { "r30", offsetof(CPUPPCState, gpr[30]) }, - { "r31", offsetof(CPUPPCState, gpr[31]) }, - /* Floating point registers */ - { "f0", offsetof(CPUPPCState, fpr[0]) }, - { "f1", offsetof(CPUPPCState, fpr[1]) }, - { "f2", offsetof(CPUPPCState, fpr[2]) }, - { "f3", offsetof(CPUPPCState, fpr[3]) }, - { "f4", offsetof(CPUPPCState, fpr[4]) }, - { "f5", offsetof(CPUPPCState, fpr[5]) }, - { "f6", offsetof(CPUPPCState, fpr[6]) }, - { "f7", offsetof(CPUPPCState, fpr[7]) }, - { "f8", offsetof(CPUPPCState, fpr[8]) }, - { "f9", offsetof(CPUPPCState, fpr[9]) }, - { "f10", offsetof(CPUPPCState, fpr[10]) }, - { "f11", offsetof(CPUPPCState, fpr[11]) }, - { "f12", offsetof(CPUPPCState, fpr[12]) }, - { "f13", offsetof(CPUPPCState, fpr[13]) }, - { "f14", offsetof(CPUPPCState, fpr[14]) }, - { "f15", offsetof(CPUPPCState, fpr[15]) }, - { "f16", offsetof(CPUPPCState, fpr[16]) }, - { "f17", offsetof(CPUPPCState, fpr[17]) }, - { "f18", offsetof(CPUPPCState, fpr[18]) }, - { "f19", offsetof(CPUPPCState, fpr[19]) }, - { "f20", offsetof(CPUPPCState, fpr[20]) }, - { "f21", offsetof(CPUPPCState, fpr[21]) }, - { "f22", offsetof(CPUPPCState, fpr[22]) }, - { "f23", offsetof(CPUPPCState, fpr[23]) }, - { "f24", offsetof(CPUPPCState, fpr[24]) }, - { "f25", offsetof(CPUPPCState, fpr[25]) }, - { "f26", offsetof(CPUPPCState, fpr[26]) }, - { "f27", offsetof(CPUPPCState, fpr[27]) }, - { "f28", offsetof(CPUPPCState, fpr[28]) }, - { "f29", offsetof(CPUPPCState, fpr[29]) }, - { "f30", offsetof(CPUPPCState, fpr[30]) }, - { "f31", offsetof(CPUPPCState, fpr[31]) }, - { "fpscr", offsetof(CPUPPCState, fpscr) }, - /* Next instruction pointer */ - { "nip|pc", offsetof(CPUPPCState, nip) }, - { "lr", offsetof(CPUPPCState, lr) }, - { "ctr", offsetof(CPUPPCState, ctr) }, - { "decr", 0, &monitor_get_decr, }, - { "ccr", 0, &monitor_get_ccr, }, - /* Machine state register */ - { "msr", 0, &monitor_get_msr, }, - { "xer", 0, &monitor_get_xer, }, - { "tbu", 0, &monitor_get_tbu, }, - { "tbl", 0, &monitor_get_tbl, }, - /* Segment registers */ - { "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) }, - { "sr0", offsetof(CPUPPCState, sr[0]) }, - { "sr1", offsetof(CPUPPCState, sr[1]) }, - { "sr2", offsetof(CPUPPCState, sr[2]) }, - { "sr3", offsetof(CPUPPCState, sr[3]) }, - { "sr4", offsetof(CPUPPCState, sr[4]) }, - { "sr5", offsetof(CPUPPCState, sr[5]) }, - { "sr6", offsetof(CPUPPCState, sr[6]) }, - { "sr7", offsetof(CPUPPCState, sr[7]) }, - { "sr8", offsetof(CPUPPCState, sr[8]) }, - { "sr9", offsetof(CPUPPCState, sr[9]) }, - { "sr10", offsetof(CPUPPCState, sr[10]) }, - { "sr11", offsetof(CPUPPCState, sr[11]) }, - { "sr12", offsetof(CPUPPCState, sr[12]) }, - { "sr13", offsetof(CPUPPCState, sr[13]) }, - { "sr14", offsetof(CPUPPCState, sr[14]) }, - { "sr15", offsetof(CPUPPCState, sr[15]) }, - /* Too lazy to put BATs... */ - { "pvr", offsetof(CPUPPCState, spr[SPR_PVR]) }, - - { "srr0", offsetof(CPUPPCState, spr[SPR_SRR0]) }, - { "srr1", offsetof(CPUPPCState, spr[SPR_SRR1]) }, - { "dar", offsetof(CPUPPCState, spr[SPR_DAR]) }, - { "dsisr", offsetof(CPUPPCState, spr[SPR_DSISR]) }, - { "cfar", offsetof(CPUPPCState, spr[SPR_CFAR]) }, - { "sprg0", offsetof(CPUPPCState, spr[SPR_SPRG0]) }, - { "sprg1", offsetof(CPUPPCState, spr[SPR_SPRG1]) }, - { "sprg2", offsetof(CPUPPCState, spr[SPR_SPRG2]) }, - { "sprg3", offsetof(CPUPPCState, spr[SPR_SPRG3]) }, - { "sprg4", offsetof(CPUPPCState, spr[SPR_SPRG4]) }, - { "sprg5", offsetof(CPUPPCState, spr[SPR_SPRG5]) }, - { "sprg6", offsetof(CPUPPCState, spr[SPR_SPRG6]) }, - { "sprg7", offsetof(CPUPPCState, spr[SPR_SPRG7]) }, - { "pid", offsetof(CPUPPCState, spr[SPR_BOOKE_PID]) }, - { "csrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR0]) }, - { "csrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR1]) }, - { "esr", offsetof(CPUPPCState, spr[SPR_BOOKE_ESR]) }, - { "dear", offsetof(CPUPPCState, spr[SPR_BOOKE_DEAR]) }, - { "mcsr", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSR]) }, - { "tsr", offsetof(CPUPPCState, spr[SPR_BOOKE_TSR]) }, - { "tcr", offsetof(CPUPPCState, spr[SPR_BOOKE_TCR]) }, - { "vrsave", offsetof(CPUPPCState, spr[SPR_VRSAVE]) }, - { "pir", offsetof(CPUPPCState, spr[SPR_BOOKE_PIR]) }, - { "mcsrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR0]) }, - { "mcsrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR1]) }, - { "decar", offsetof(CPUPPCState, spr[SPR_BOOKE_DECAR]) }, - { "ivpr", offsetof(CPUPPCState, spr[SPR_BOOKE_IVPR]) }, - { "epcr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPCR]) }, - { "sprg8", offsetof(CPUPPCState, spr[SPR_BOOKE_SPRG8]) }, - { "ivor0", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR0]) }, - { "ivor1", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR1]) }, - { "ivor2", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR2]) }, - { "ivor3", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR3]) }, - { "ivor4", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR4]) }, - { "ivor5", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR5]) }, - { "ivor6", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR6]) }, - { "ivor7", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR7]) }, - { "ivor8", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR8]) }, - { "ivor9", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR9]) }, - { "ivor10", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR10]) }, - { "ivor11", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR11]) }, - { "ivor12", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR12]) }, - { "ivor13", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR13]) }, - { "ivor14", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR14]) }, - { "ivor15", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR15]) }, - { "ivor32", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR32]) }, - { "ivor33", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR33]) }, - { "ivor34", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR34]) }, - { "ivor35", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR35]) }, - { "ivor36", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR36]) }, - { "ivor37", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR37]) }, - { "mas0", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS0]) }, - { "mas1", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS1]) }, - { "mas2", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS2]) }, - { "mas3", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS3]) }, - { "mas4", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS4]) }, - { "mas6", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS6]) }, - { "mas7", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS7]) }, - { "mmucfg", offsetof(CPUPPCState, spr[SPR_MMUCFG]) }, - { "tlb0cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB0CFG]) }, - { "tlb1cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB1CFG]) }, - { "epr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPR]) }, - { "eplc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPLC]) }, - { "epsc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPSC]) }, - { "svr", offsetof(CPUPPCState, spr[SPR_E500_SVR]) }, - { "mcar", offsetof(CPUPPCState, spr[SPR_Exxx_MCAR]) }, - { "pid1", offsetof(CPUPPCState, spr[SPR_BOOKE_PID1]) }, - { "pid2", offsetof(CPUPPCState, spr[SPR_BOOKE_PID2]) }, - { "hid0", offsetof(CPUPPCState, spr[SPR_HID0]) }, - -#elif defined(TARGET_SPARC) - { "g0", offsetof(CPUSPARCState, gregs[0]) }, - { "g1", offsetof(CPUSPARCState, gregs[1]) }, - { "g2", offsetof(CPUSPARCState, gregs[2]) }, - { "g3", offsetof(CPUSPARCState, gregs[3]) }, - { "g4", offsetof(CPUSPARCState, gregs[4]) }, - { "g5", offsetof(CPUSPARCState, gregs[5]) }, - { "g6", offsetof(CPUSPARCState, gregs[6]) }, - { "g7", offsetof(CPUSPARCState, gregs[7]) }, - { "o0", 0, monitor_get_reg }, - { "o1", 1, monitor_get_reg }, - { "o2", 2, monitor_get_reg }, - { "o3", 3, monitor_get_reg }, - { "o4", 4, monitor_get_reg }, - { "o5", 5, monitor_get_reg }, - { "o6", 6, monitor_get_reg }, - { "o7", 7, monitor_get_reg }, - { "l0", 8, monitor_get_reg }, - { "l1", 9, monitor_get_reg }, - { "l2", 10, monitor_get_reg }, - { "l3", 11, monitor_get_reg }, - { "l4", 12, monitor_get_reg }, - { "l5", 13, monitor_get_reg }, - { "l6", 14, monitor_get_reg }, - { "l7", 15, monitor_get_reg }, - { "i0", 16, monitor_get_reg }, - { "i1", 17, monitor_get_reg }, - { "i2", 18, monitor_get_reg }, - { "i3", 19, monitor_get_reg }, - { "i4", 20, monitor_get_reg }, - { "i5", 21, monitor_get_reg }, - { "i6", 22, monitor_get_reg }, - { "i7", 23, monitor_get_reg }, - { "pc", offsetof(CPUSPARCState, pc) }, - { "npc", offsetof(CPUSPARCState, npc) }, - { "y", offsetof(CPUSPARCState, y) }, -#ifndef TARGET_SPARC64 - { "psr", 0, &monitor_get_psr, }, - { "wim", offsetof(CPUSPARCState, wim) }, -#endif - { "tbr", offsetof(CPUSPARCState, tbr) }, - { "fsr", offsetof(CPUSPARCState, fsr) }, - { "f0", offsetof(CPUSPARCState, fpr[0].l.upper) }, - { "f1", offsetof(CPUSPARCState, fpr[0].l.lower) }, - { "f2", offsetof(CPUSPARCState, fpr[1].l.upper) }, - { "f3", offsetof(CPUSPARCState, fpr[1].l.lower) }, - { "f4", offsetof(CPUSPARCState, fpr[2].l.upper) }, - { "f5", offsetof(CPUSPARCState, fpr[2].l.lower) }, - { "f6", offsetof(CPUSPARCState, fpr[3].l.upper) }, - { "f7", offsetof(CPUSPARCState, fpr[3].l.lower) }, - { "f8", offsetof(CPUSPARCState, fpr[4].l.upper) }, - { "f9", offsetof(CPUSPARCState, fpr[4].l.lower) }, - { "f10", offsetof(CPUSPARCState, fpr[5].l.upper) }, - { "f11", offsetof(CPUSPARCState, fpr[5].l.lower) }, - { "f12", offsetof(CPUSPARCState, fpr[6].l.upper) }, - { "f13", offsetof(CPUSPARCState, fpr[6].l.lower) }, - { "f14", offsetof(CPUSPARCState, fpr[7].l.upper) }, - { "f15", offsetof(CPUSPARCState, fpr[7].l.lower) }, - { "f16", offsetof(CPUSPARCState, fpr[8].l.upper) }, - { "f17", offsetof(CPUSPARCState, fpr[8].l.lower) }, - { "f18", offsetof(CPUSPARCState, fpr[9].l.upper) }, - { "f19", offsetof(CPUSPARCState, fpr[9].l.lower) }, - { "f20", offsetof(CPUSPARCState, fpr[10].l.upper) }, - { "f21", offsetof(CPUSPARCState, fpr[10].l.lower) }, - { "f22", offsetof(CPUSPARCState, fpr[11].l.upper) }, - { "f23", offsetof(CPUSPARCState, fpr[11].l.lower) }, - { "f24", offsetof(CPUSPARCState, fpr[12].l.upper) }, - { "f25", offsetof(CPUSPARCState, fpr[12].l.lower) }, - { "f26", offsetof(CPUSPARCState, fpr[13].l.upper) }, - { "f27", offsetof(CPUSPARCState, fpr[13].l.lower) }, - { "f28", offsetof(CPUSPARCState, fpr[14].l.upper) }, - { "f29", offsetof(CPUSPARCState, fpr[14].l.lower) }, - { "f30", offsetof(CPUSPARCState, fpr[15].l.upper) }, - { "f31", offsetof(CPUSPARCState, fpr[15].l.lower) }, -#ifdef TARGET_SPARC64 - { "f32", offsetof(CPUSPARCState, fpr[16]) }, - { "f34", offsetof(CPUSPARCState, fpr[17]) }, - { "f36", offsetof(CPUSPARCState, fpr[18]) }, - { "f38", offsetof(CPUSPARCState, fpr[19]) }, - { "f40", offsetof(CPUSPARCState, fpr[20]) }, - { "f42", offsetof(CPUSPARCState, fpr[21]) }, - { "f44", offsetof(CPUSPARCState, fpr[22]) }, - { "f46", offsetof(CPUSPARCState, fpr[23]) }, - { "f48", offsetof(CPUSPARCState, fpr[24]) }, - { "f50", offsetof(CPUSPARCState, fpr[25]) }, - { "f52", offsetof(CPUSPARCState, fpr[26]) }, - { "f54", offsetof(CPUSPARCState, fpr[27]) }, - { "f56", offsetof(CPUSPARCState, fpr[28]) }, - { "f58", offsetof(CPUSPARCState, fpr[29]) }, - { "f60", offsetof(CPUSPARCState, fpr[30]) }, - { "f62", offsetof(CPUSPARCState, fpr[31]) }, - { "asi", offsetof(CPUSPARCState, asi) }, - { "pstate", offsetof(CPUSPARCState, pstate) }, - { "cansave", offsetof(CPUSPARCState, cansave) }, - { "canrestore", offsetof(CPUSPARCState, canrestore) }, - { "otherwin", offsetof(CPUSPARCState, otherwin) }, - { "wstate", offsetof(CPUSPARCState, wstate) }, - { "cleanwin", offsetof(CPUSPARCState, cleanwin) }, - { "fprs", offsetof(CPUSPARCState, fprs) }, -#endif -#endif - { NULL }, -}; - -static void GCC_FMT_ATTR(2, 3) QEMU_NORETURN -expr_error(Monitor *mon, const char *fmt, ...) -{ - va_list ap; - va_start(ap, fmt); - monitor_vprintf(mon, fmt, ap); - monitor_printf(mon, "\n"); - va_end(ap); - siglongjmp(expr_env, 1); -} - -/* return 0 if OK, -1 if not found */ -static int get_monitor_def(target_long *pval, const char *name) -{ - const MonitorDef *md; - void *ptr; - - for(md = monitor_defs; md->name != NULL; md++) { - if (compare_cmd(name, md->name)) { - if (md->get_value) { - *pval = md->get_value(md, md->offset); - } else { - CPUArchState *env = mon_get_cpu(); - ptr = (uint8_t *)env + md->offset; - switch(md->type) { - case MD_I32: - *pval = *(int32_t *)ptr; - break; - case MD_TLONG: - *pval = *(target_long *)ptr; - break; - default: - *pval = 0; - break; - } - } - return 0; - } - } - return -1; -} - -static void next(void) -{ - if (*pch != '\0') { - pch++; - while (qemu_isspace(*pch)) - pch++; - } -} - -static int64_t expr_sum(Monitor *mon); - -static int64_t expr_unary(Monitor *mon) -{ - int64_t n; - char *p; - int ret; - - switch(*pch) { - case '+': - next(); - n = expr_unary(mon); - break; - case '-': - next(); - n = -expr_unary(mon); - break; - case '~': - next(); - n = ~expr_unary(mon); - break; - case '(': - next(); - n = expr_sum(mon); - if (*pch != ')') { - expr_error(mon, "')' expected"); - } - next(); - break; - case '\'': - pch++; - if (*pch == '\0') - expr_error(mon, "character constant expected"); - n = *pch; - pch++; - if (*pch != '\'') - expr_error(mon, "missing terminating \' character"); - next(); - break; - case '$': - { - char buf[128], *q; - target_long reg=0; - - pch++; - q = buf; - while ((*pch >= 'a' && *pch <= 'z') || - (*pch >= 'A' && *pch <= 'Z') || - (*pch >= '0' && *pch <= '9') || - *pch == '_' || *pch == '.') { - if ((q - buf) < sizeof(buf) - 1) - *q++ = *pch; - pch++; - } - while (qemu_isspace(*pch)) - pch++; - *q = 0; - ret = get_monitor_def(®, buf); - if (ret < 0) - expr_error(mon, "unknown register"); - n = reg; - } - break; - case '\0': - expr_error(mon, "unexpected end of expression"); - n = 0; - break; - default: - errno = 0; - n = strtoull(pch, &p, 0); - if (errno == ERANGE) { - expr_error(mon, "number too large"); - } - if (pch == p) { - expr_error(mon, "invalid char '%c' in expression", *p); - } - pch = p; - while (qemu_isspace(*pch)) - pch++; - break; - } - return n; -} - - -static int64_t expr_prod(Monitor *mon) -{ - int64_t val, val2; - int op; - - val = expr_unary(mon); - for(;;) { - op = *pch; - if (op != '*' && op != '/' && op != '%') - break; - next(); - val2 = expr_unary(mon); - switch(op) { - default: - case '*': - val *= val2; - break; - case '/': - case '%': - if (val2 == 0) - expr_error(mon, "division by zero"); - if (op == '/') - val /= val2; - else - val %= val2; - break; - } - } - return val; -} - -static int64_t expr_logic(Monitor *mon) -{ - int64_t val, val2; - int op; - - val = expr_prod(mon); - for(;;) { - op = *pch; - if (op != '&' && op != '|' && op != '^') - break; - next(); - val2 = expr_prod(mon); - switch(op) { - default: - case '&': - val &= val2; - break; - case '|': - val |= val2; - break; - case '^': - val ^= val2; - break; - } - } - return val; -} - -static int64_t expr_sum(Monitor *mon) -{ - int64_t val, val2; - int op; - - val = expr_logic(mon); - for(;;) { - op = *pch; - if (op != '+' && op != '-') - break; - next(); - val2 = expr_logic(mon); - if (op == '+') - val += val2; - else - val -= val2; - } - return val; -} - -int get_expr(Monitor *mon, int64_t *pval, const char **pp) -{ - pch = *pp; - if (sigsetjmp(expr_env, 0)) { - *pp = pch; - return -1; - } - while (qemu_isspace(*pch)) - pch++; - *pval = expr_sum(mon); - *pp = pch; - return 0; -} - -int get_double(Monitor *mon, double *pval, const char **pp) -{ - const char *p = *pp; - char *tailp; - double d; - - d = strtod(p, &tailp); - if (tailp == p) { - monitor_printf(mon, "Number expected\n"); - return -1; - } - if (d != d || d - d != 0) { - /* NaN or infinity */ - monitor_printf(mon, "Bad number\n"); - return -1; - } - *pval = d; - *pp = tailp; - return 0; -} - /* * Store the command-name in cmdname, and return a pointer to * the remaining of the command string. @@ -3859,10 +2895,10 @@ static void sortcmdlist(void) int array_num; int elem_size = sizeof(mon_cmd_t); - array_num = sizeof(mon_cmds)/elem_size-1; + array_num = sizeof_mon_cmds/elem_size-1; qsort((void *)mon_cmds, array_num, elem_size, compare_mon_cmd); - array_num = sizeof(info_cmds)/elem_size-1; + array_num = sizeof_info_cmds/elem_size-1; qsort((void *)info_cmds, array_num, elem_size, compare_mon_cmd); }