From patchwork Mon Jun 30 23:09:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 365800 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3682E14010F for ; Tue, 1 Jul 2014 09:11:34 +1000 (EST) Received: from localhost ([::1]:37009 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kjU-0006lz-7d for incoming@patchwork.ozlabs.org; Mon, 30 Jun 2014 19:11:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52981) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kid-0005Y9-Rm for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kiY-00039l-DW for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:39 -0400 Received: from mail-ob0-f176.google.com ([209.85.214.176]:53907) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kiY-00039Y-8K for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:34 -0400 Received: by mail-ob0-f176.google.com with SMTP id wm4so9522017obc.7 for ; Mon, 30 Jun 2014 16:10:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZMFxvRj7TvFEfNaDMp7YJWfI3NAQPkKrc1brwWzV3Ks=; b=ENrNVA7SwUEQ78k9w3AJgc0penowLoGzjC9SMHGLmAV3cgP6wZRWOzsxzCZRLMFSIO MYYlYWQYOE2aZmurlIKBDPPVGFTsFjDCcPV/oBeXhDpHAUxoKPscu0KxNL0KM+LUOjJQ 6wlY2rGRT3r2y3hvRnU+eNrk5cVmUo50ibut5kzwlJ1qnh1LdW3ArgykUja9wNRtZU1K 9B7+GgrGxYrCHsJcdvnr3d0zjfrsslvTxdELvmiDNX2pjSUep9PgZ8gwG8r5FS8y91ip USCcXabsAY7q6GLAt+TUnbkbriLDrM9HDgGJAVJUJN5l6wmQIrxZLM0tXW/MhDIb7wZA U+gA== X-Gm-Message-State: ALoCoQnu5oBLbK4KM9mRx4Cfjtlq0sDVR6XWmQNumjxDNy9QN/zFFgmj6CAvU4xlTKBUXrYkSmtb X-Received: by 10.182.134.164 with SMTP id pl4mr46124205obb.16.1404169833906; Mon, 30 Jun 2014 16:10:33 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id cu7sm76370192oec.12.2014.06.30.16.10.31 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 16:10:32 -0700 (PDT) From: greg.bellows@linaro.org To: qemu-devel@nongnu.org Date: Mon, 30 Jun 2014 18:09:06 -0500 Message-Id: <1404169773-20264-7-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.176 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 06/33] target-arm: make arm_current_pl() return PL3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Make arm_current_pl() return PL3 for secure PL1 and monitor mode. Increase MMU modes since mmu_index is directly infered from arm_ current_pl(). Changes assertion in arm_el_is_aa64() to allow EL3. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index aba077b..1faf1e2 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -100,7 +100,7 @@ typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, struct arm_boot_info; -#define NB_MMU_MODES 2 +#define NB_MMU_MODES 4 /* We currently assume float and double are IEEE single and double precision respectively. @@ -726,7 +726,6 @@ static inline int arm_feature(CPUARMState *env, int feature) return (env->features & (1ULL << feature)) != 0; } - /* Return true if exception level below EL3 is in secure state */ static inline bool arm_is_secure_below_el3(CPUARMState *env) { @@ -767,11 +766,12 @@ static inline bool arm_is_secure(CPUARMState *env) /* Return true if the specified exception level is running in AArch64 state. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) { - /* We don't currently support EL2 or EL3, and this isn't valid for EL0 + /* We don't currently support EL2, and this isn't valid for EL0 * (if we're in EL0, is_a64() is what you want, and if we're not in EL0 * then the state of EL0 isn't well defined.) */ - assert(el == 1); + assert(el == 1 || el == 3); + /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This * is a QEMU-imposed simplification which we may wish to change later. * If we in future support EL2 and/or EL3, then the state of lower @@ -963,9 +963,12 @@ static inline int arm_current_pl(CPUARMState *env) if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { return 0; + } else if (arm_is_secure(env)) { + /* Secure PL1 and monitor mode are mapped to PL3 */ + return 3; } - /* We don't currently implement the Virtualization or TrustZone - * extensions, so PL2 and PL3 don't exist for us. + /* We currently do not implement the Virtualization extensions, so PL2 does + * not exist for us. */ return 1; }