From patchwork Mon Jun 30 23:09:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 365803 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 21E421400B5 for ; Tue, 1 Jul 2014 09:13:16 +1000 (EST) Received: from localhost ([::1]:37029 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kl7-0008LG-VK for incoming@patchwork.ozlabs.org; Mon, 30 Jun 2014 19:13:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52957) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kic-0005Y6-JR for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kiU-00037Y-1I for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:38 -0400 Received: from mail-ob0-f180.google.com ([209.85.214.180]:48309) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kiT-00037M-ST for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:29 -0400 Received: by mail-ob0-f180.google.com with SMTP id vb8so9558514obc.39 for ; Mon, 30 Jun 2014 16:10:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WbTs+b8wiBQAJccct8s6cKFmrOXWiVC6nBm9l9O7Acs=; b=So1vvzN2fI/FxpLawVU25jo+supGlIg7WsHetapNabyIb7qtPksF/hsj5HzjyYVB4o qnHH4sJLKFAka4LFDfoAR1aCPT6H0JeVuwMYyOLpdMtj/91oKZY4WkeVlaATvH7/LlhK Z/kJWKezjEj7TDKelyXYVdkO6NNAupJRp2z8+Q6uJJVTW8fuTryQ6jk9dQT1vfi0aweJ 1eYDaJQ0Z6+3HSqnki8MU25qqqBWdjQc5Wql/ZIJBgdHwPogWwh/GwQXfEpMRF8eHMxU Jh+GQWfQqr5cS7p2ptDzF2ndTCWyXivkSggfucj0/ZL9wD4U3BZfQKiuys8SnAGy52N/ 5GfQ== X-Gm-Message-State: ALoCoQn/aIZ2gwb6q2OhIW88AsSziU5FUhpejmAs7nuG465LTw12FMUT2KLyE1bOfIs7tmCeAJQI X-Received: by 10.182.241.130 with SMTP id wi2mr40491422obc.27.1404169829528; Mon, 30 Jun 2014 16:10:29 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id cu7sm76370192oec.12.2014.06.30.16.10.27 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 16:10:28 -0700 (PDT) From: greg.bellows@linaro.org To: qemu-devel@nongnu.org Date: Mon, 30 Jun 2014 18:09:04 -0500 Message-Id: <1404169773-20264-5-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.180 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Sergey Fedorov , Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 04/33] target-arm: add arm_is_secure() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler arm_is_secure() function allows to determine CPU security state if the CPU implements Security Extensions/EL3. arm_is_secure_below_el3() returns true if CPU is in secure state below EL3. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index ffc51f2..aba077b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -726,6 +726,44 @@ static inline int arm_feature(CPUARMState *env, int feature) return (env->features & (1ULL << feature)) != 0; } + +/* Return true if exception level below EL3 is in secure state */ +static inline bool arm_is_secure_below_el3(CPUARMState *env) +{ +#if !defined(CONFIG_USER_ONLY) + if (arm_feature(env, ARM_FEATURE_EL3)) { + return !(env->cp15.scr_el3 & SCR_NS); + } else if (arm_feature(env, ARM_FEATURE_EL2)) { + return false; + } else { + /* IMPDEF: QEMU defaults to non-secure */ + return false; + } +#else + return false; +#endif +} + +/* Return true if the processor is in secure state */ +static inline bool arm_is_secure(CPUARMState *env) +{ +#if !defined(CONFIG_USER_ONLY) + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (env->aarch64 && extract32(env->pstate, 2, 2) == 3) { + /* CPU currently in Aarch64 state and EL3 */ + return true; + } else if (!env->aarch64 && + (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { + /* CPU currently in Aarch32 state and monitor mode */ + return true; + } + } + return arm_is_secure_below_el3(env); +#else + return false; +#endif +} + /* Return true if the specified exception level is running in AArch64 state. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) {