From patchwork Mon Jun 30 23:09:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 365814 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 595C9140096 for ; Tue, 1 Jul 2014 09:19:20 +1000 (EST) Received: from localhost ([::1]:37121 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kr0-0005yE-GM for incoming@patchwork.ozlabs.org; Mon, 30 Jun 2014 19:19:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54191) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kjZ-0006vG-7s for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kjT-0003yg-RF for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:37 -0400 Received: from mail-ob0-f182.google.com ([209.85.214.182]:36322) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kjT-0003yJ-C0 for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:31 -0400 Received: by mail-ob0-f182.google.com with SMTP id nu7so9794470obb.27 for ; Mon, 30 Jun 2014 16:11:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DmkD7TrT5hToBri77Ijo6V7JR3mvn7TeQSxBqVdotl0=; b=Hq+lDDgtk46obNPE0ZgLB1mCDQDwleDya+os3NCvnMUUyTqQRoLqHJBEvZgKM0gse+ gzDSHxJBMAmH4zu4HE4dgel0bBCYYc+YPFf6rfs3QmZsg/dRPq9y7LjSmu/abivvzWVp rgb9IGc4DqZ4+7Welc06bHE+S3qVD4BtMLk0oJROwtbf9sFpJXK58dRLOIiJH9K1XVoW Quaee1nljSYQIaxlpL/j8NlhEYXcb3qwJ0W5lgfCTKSr/zkOXXueRv/qzlAZSxz9XhND 15DBPiA5vq6FTayJnZols56uwmUfV36NBLfQzzpR2N72C45h5rycdaXa3+k1TtMxjJSi xULg== X-Gm-Message-State: ALoCoQkdbXhyvVnM4pgzIjDDyP3yyyFXi4Ybx81GBSGfoq74IE58sxHjrlRdNXN1vsTQ4yZ3wP2b X-Received: by 10.182.115.199 with SMTP id jq7mr6935575obb.70.1404169891089; Mon, 30 Jun 2014 16:11:31 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id cu7sm76370192oec.12.2014.06.30.16.11.29 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 16:11:30 -0700 (PDT) From: greg.bellows@linaro.org To: qemu-devel@nongnu.org Date: Mon, 30 Jun 2014 18:09:32 -0500 Message-Id: <1404169773-20264-33-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.182 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 32/33] target-arm: make c13 cp regs banked (FCSEIDR, ...) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows -------------- v3 -> v4 - Fix tpidrprw mapping Signed-off-by: Greg Bellows --- target-arm/cpu.h | 45 ++++++++++++++++++++++++++++++++++++++++----- target-arm/helper.c | 27 +++++++++++++++++---------- 2 files changed, 57 insertions(+), 15 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index aade869..3c96131 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -322,11 +322,46 @@ typedef struct CPUARMState { uint64_t vbar_el[4]; }; uint64_t mvbar; /* (monitor) vector base address register */ - uint32_t c13_fcse; /* FCSE PID. */ - uint64_t contextidr_el1; /* Context ID. */ - uint64_t tpidr_el0; /* User RW Thread register. */ - uint64_t tpidrro_el0; /* User RO Thread register. */ - uint64_t tpidr_el1; /* Privileged Thread register. */ + struct { /* FCSE PID. */ + uint32_t c13_fcseidr_ns; + uint32_t c13_fcseidr_s; + }; + union { /* Context ID. */ + struct { + uint64_t contextidr_ns; + uint64_t contextidr_s; + }; + struct { + uint64_t contextidr_el1; + }; + }; + union { /* User RW Thread register. */ + struct { + uint64_t tpidrurw_ns; + uint64_t tpidrurw_s; + }; + struct { + uint64_t tpidr_el0; + }; + }; + union { /* User RO Thread register. */ + struct { + uint64_t tpidruro_ns; + uint64_t tpidruro_s; + }; + struct { + uint64_t tpidrro_el0; + }; + }; + union { /* Privileged Thread register. */ + struct { + uint64_t tpidrprw_ns; + uint64_t tpidrprw_s; + }; + struct { + uint64_t tpidr_el1; + }; + }; uint64_t c14_cntfrq; /* Counter Frequency register */ uint64_t c14_cntkctl; /* Timer Control register */ ARMGenericTimer c14_timer[NUM_GTIMERS]; diff --git a/target-arm/helper.c b/target-arm/helper.c index 1a07124..3bc55fe 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -396,12 +396,15 @@ static const ARMCPRegInfo cp_reginfo[] = { { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), + .access = PL1_RW, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.c13_fcseidr_s), + offsetof(CPUARMState, cp15.c13_fcseidr_ns) }, .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.contextidr_s), + offsetof(CPUARMState, cp15.contextidr_ns) }, .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, REGINFO_SENTINEL }; @@ -889,21 +892,25 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = { .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 }, { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, - .access = PL0_RW, - .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0), - .resetfn = arm_cp_reset_ignore }, + .access = PL0_RW, .resetfn = arm_cp_reset_ignore, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), + offsetoflow32(CPUARMState, cp15.tpidrurw_ns) } }, { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, .access = PL0_R|PL1_W, .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 }, { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, - .access = PL0_R|PL1_W, - .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0), - .resetfn = arm_cp_reset_ignore }, - { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH, + .access = PL0_R|PL1_W, .resetfn = arm_cp_reset_ignore, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), + offsetoflow32(CPUARMState, cp15.tpidruro_ns) } }, + { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 }, + { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4, + .access = PL1_RW, .resetfn = arm_cp_reset_ignore, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), + offsetoflow32(CPUARMState, cp15.tpidrprw_ns) } }, REGINFO_SENTINEL }; @@ -4615,7 +4622,7 @@ static inline int get_phys_addr(CPUARMState *env, target_ulong address, /* Fast Context Switch Extension. */ if (address < 0x02000000) - address += env->cp15.c13_fcse; + address += A32_BANKED_CURRENT_REG_GET(env, c13_fcseidr); if ((sctlr & SCTLR_M) == 0) { /* MMU/MPU disabled. */