From patchwork Mon Jun 30 23:09:17 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 365820 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 521E4140096 for ; Tue, 1 Jul 2014 09:21:56 +1000 (EST) Received: from localhost ([::1]:37151 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1ktV-0000Hm-VU for incoming@patchwork.ozlabs.org; Mon, 30 Jun 2014 19:21:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53453) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kj2-00062o-Gr for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kix-0003Rb-LQ for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:04 -0400 Received: from mail-oa0-f42.google.com ([209.85.219.42]:56954) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kix-0003RM-Eb for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:59 -0400 Received: by mail-oa0-f42.google.com with SMTP id eb12so9737542oac.29 for ; Mon, 30 Jun 2014 16:10:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1BpKTcoTRyGnhczYUONupcpVtUQNkK4huGUpksUrDTs=; b=YcxIo1eZki1F60vDnpNTSBt0shfbZev8TfIPvEO8PyiRVuJOmvrSZh1MJgt2/qcKK8 iZkORDkEv4CPEotJ4Y+96GW4rYnTai5TLWXdu1brLgfp7XScdsty6uFFQgUD1ayNg3jW +YOb7tCQx/2GSRsV8/YZN301Da1oy1HmzWUBgWdldLReww7o910ddflh96uzPqO6IJxf 9ZLEw+C97MXQBB2wohC/QZmBdDXsuUpo3suJ6XqhzNsELH36zLzEVAfdyij0cTznAB6C 1Pyns+M+Awc+ja91o78uUb1VbjNmej6U6OE4VdIdgFB0dqA1BlNM6gfVsxZziTVU3iTK e3Sg== X-Gm-Message-State: ALoCoQm/oBG6Ls2xfMyDeVTdMZhfqdKmMZo4DCdPKYL8W0lTZiNis2J/b6tKeYQnUCgSuMm7CrOM X-Received: by 10.60.56.83 with SMTP id y19mr6535633oep.74.1404169859080; Mon, 30 Jun 2014 16:10:59 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id cu7sm76370192oec.12.2014.06.30.16.10.56 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 16:10:57 -0700 (PDT) From: greg.bellows@linaro.org To: qemu-devel@nongnu.org Date: Mon, 30 Jun 2014 18:09:17 -0500 Message-Id: <1404169773-20264-18-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.219.42 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Sergey Fedorov , Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 17/33] target-arm: add MVBAR support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Use MVBAR register as exception vector base address for exceptions taken to CPU monitor mode. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 1 + target-arm/helper.c | 15 +++++++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7aecb0f..a2dab08 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -212,6 +212,7 @@ typedef struct CPUARMState { uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; uint64_t vbar_el[4]; /* vector base address register */ + uint64_t mvbar; /* (monitor) vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint64_t contextidr_el1; /* Context ID. */ uint64_t tpidr_el0; /* User RW Thread register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 7a2c861..d3dbf33 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2297,6 +2297,9 @@ static const ARMCPRegInfo v7_el3_cp_reginfo[] = { .access = PL3_RW | PL1_R, .resetvalue = 0, .writefn = nsacr_write, .readfn = nsacr_read, .fieldoffset = offsetof(CPUARMState, cp15.c1_nsacr) }, + { .name = "MVBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, REGINFO_SENTINEL }; @@ -3872,16 +3875,16 @@ void arm_cpu_do_interrupt(CPUState *cs) cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ } - /* High vectors. */ - if (env->cp15.c1_sys & SCTLR_V) { - /* when enabled, base address cannot be remapped. */ + + if (new_mode == ARM_CPU_MODE_MON) { + addr += env->cp15.mvbar; + } else if (env->cp15.c1_sys & SCTLR_V) { + /* High vectors. When enabled, base address cannot be remapped. */ addr += 0xffff0000; } else { /* ARM v7 architectures provide a vector base address register to remap * the interrupt vector table. - * This register is only followed in non-monitor mode, and has a secure - * and un-secure copy. Since the cpu is always in a un-secure operation - * and is never in monitor mode this feature is always active. + * This register is only followed in non-monitor mode, and is banked. * Note: only bits 31:5 are valid. */ addr += env->cp15.vbar_el[1];