From patchwork Mon Jun 30 23:09:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 365816 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 9BA841400B5 for ; Tue, 1 Jul 2014 09:20:10 +1000 (EST) Received: from localhost ([::1]:37130 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kro-0007Gu-Mz for incoming@patchwork.ozlabs.org; Mon, 30 Jun 2014 19:20:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53409) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kj0-0005z5-HV for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kiv-0003Q8-Er for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:02 -0400 Received: from mail-ob0-f169.google.com ([209.85.214.169]:38450) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kiv-0003Pr-2i for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:57 -0400 Received: by mail-ob0-f169.google.com with SMTP id wp18so9723832obc.28 for ; Mon, 30 Jun 2014 16:10:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PEK4PrQmDuGrgtuCVF5Zn1bgg9aVOL5t9s88yeftWmg=; b=EGqdYPTyyKzdr5Dq75NPY4bl9ay/qX2agLjNeg1JWE9odde7mSRK6uoUqJWqFsUzF3 VGEQwd7Bfz6RgrAXOm+KtiGZPjukhW7uL1v/YNue4CX0gMgwII+3TtBdruOnCv3mhfjd wEB/pjFmrgKpLkOeC2PJz76AlJNKQeStAPS3y8ew6JdiQTWcRcz1/AbrS9pskRJxn+68 Ez3vYNvB89JzRS2tjoVIkPtY2VO5xQBhsbvYsSyPSaUVoVtnO/QugnjWElEZ53ZD6QQl 3R5OWfcCbo69VjxGZIhuPtB3wB+SQM0aGDtnU+bxhwR3YIBlKcsA1m9qNVXURiDZwKJJ L6Yg== X-Gm-Message-State: ALoCoQljyFtMcfA2HvG7B/s1ejAszYXBMqQJg0CFkmhzHTTAtYDS+YlgvhdZGm9ppKaxB4AU8fj8 X-Received: by 10.60.103.206 with SMTP id fy14mr45347677oeb.21.1404169856733; Mon, 30 Jun 2014 16:10:56 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id cu7sm76370192oec.12.2014.06.30.16.10.54 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 16:10:55 -0700 (PDT) From: greg.bellows@linaro.org To: qemu-devel@nongnu.org Date: Mon, 30 Jun 2014 18:09:16 -0500 Message-Id: <1404169773-20264-17-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.169 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Sergey Fedorov , Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 16/33] target-arm: add SDER definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Sergey Fedorov Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 1 + target-arm/helper.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 4625088..7aecb0f 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -182,6 +182,7 @@ typedef struct CPUARMState { uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint32_t c1_scr; /* secure config register. */ + uint32_t c1_sder; /* Secure debug enable register. */ uint32_t c1_nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 6342dbf..7a2c861 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2290,6 +2290,9 @@ static const ARMCPRegInfo v7_el3_cp_reginfo[] = { { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), .resetvalue = 0, }, + { .name = "SDER", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.c1_sder) }, { .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2, .access = PL3_RW | PL1_R, .resetvalue = 0, .writefn = nsacr_write, .readfn = nsacr_read,