From patchwork Mon Jun 30 23:09:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 365808 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C55EF1400AB for ; Tue, 1 Jul 2014 09:16:42 +1000 (EST) Received: from localhost ([::1]:37096 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1koS-0003RZ-UT for incoming@patchwork.ozlabs.org; Mon, 30 Jun 2014 19:16:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53266) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kit-0005ng-Mi for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kio-0003LU-Lv for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:55 -0400 Received: from mail-oa0-f49.google.com ([209.85.219.49]:35619) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kio-0003LK-Hp for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:50 -0400 Received: by mail-oa0-f49.google.com with SMTP id i7so9605816oag.36 for ; Mon, 30 Jun 2014 16:10:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+TJQmoYwfrOaO86REjIYMaicca0dYU2w06gZHzlKmOk=; b=ZrHG3xV8BAinliFnk9QegTAFZzMmeMr8i4zr44hLbPydqO9QgyMkytUEJ0KjXFzfiv vKIqVLORx3qQ09TGc6h/jt0ltmy7jJaElPM563jVNLign61IGmO6SYViQ7JX8v1lMOFk G2Ft7S6C4ezpzYD/EtaWO5PdERd4NxgdYNQOQrQSICCZejTeca0FhLGkY7D81VQEnwVk hmMSDO1O2njzvSQiL+j7N1Cc11Y7pTKBmS+YggDqVCgHh0AaQCisNI8BdTzGuOSvysTL eoz5kuNzuac3IzTd7lWdqHY5IC35vA5Sxf8/ZslosvlriuJVUMFypGdB7xOTap+frnWp egdA== X-Gm-Message-State: ALoCoQl8MUqgfry5gJGrUth14zkOABOw+iIx+F7nM33cw/0CtAMJiGEkMnYeq6aUbvEJAz2IzAFc X-Received: by 10.60.47.77 with SMTP id b13mr6157561oen.83.1404169850278; Mon, 30 Jun 2014 16:10:50 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id cu7sm76370192oec.12.2014.06.30.16.10.48 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 16:10:49 -0700 (PDT) From: greg.bellows@linaro.org To: qemu-devel@nongnu.org Date: Mon, 30 Jun 2014 18:09:13 -0500 Message-Id: <1404169773-20264-14-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.219.49 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Sergey Fedorov , Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 13/33] target-arm: implement IRQ/FIQ routing to Monitor mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 456b7e7..7a878e9 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3720,12 +3720,21 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Disable IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I; offset = 4; + if (env->cp15.scr_el3 & SCR_IRQ) { + /* IRQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + mask |= CPSR_F; + } break; case EXCP_FIQ: new_mode = ARM_CPU_MODE_FIQ; addr = 0x1c; /* Disable FIQ, IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I | CPSR_F; + if (env->cp15.scr_el3 & SCR_FIQ) { + /* FIQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + } offset = 4; break; case EXCP_SMC: