From patchwork Mon Jun 30 23:09:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 365804 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id EA63D1400AB for ; Tue, 1 Jul 2014 09:13:31 +1000 (EST) Received: from localhost ([::1]:37032 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1klN-0000Fo-UF for incoming@patchwork.ozlabs.org; Mon, 30 Jun 2014 19:13:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53136) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kin-0005cb-1o for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kih-0003GG-Qz for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:48 -0400 Received: from mail-ob0-f172.google.com ([209.85.214.172]:63318) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kih-0003F4-Ai for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:43 -0400 Received: by mail-ob0-f172.google.com with SMTP id uy5so9734289obc.31 for ; Mon, 30 Jun 2014 16:10:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zJfXPw0luXtIGYbBDT/gw63uSK72V8wmzSNg6pWsFtU=; b=V124lqIMXjZ6/PnxNf/MuUDvlZxWpoSau193By5g33CUoTRMOPNyC0rwZZaaTE6kMk kbkfdmNmcRh5i5BZXxUmT34U/0P522yAlyJl8rf0TBPSatvdsGdxu2wUD+8aC+OH85NQ f3LLV/ho7Y2cACtg0oYJiCJGzneNHuf/UqFSY678UWavefbRUbfi8HxIyloJcZk/Z0PN wowlvblhOVqj9B09OBB5eJUkTOAIOcqlUqp4r7rIP0THhuKJsyHixZr8WmNqtT6DbQOk iKE3tAtSEnUK6gbv4nKaFT+Rd0jLABzsDqXrByA/N4yNyhlmwD0IMIG0Z4WNAPyiIIiX BtkQ== X-Gm-Message-State: ALoCoQllzx5gKN/k3P9UFLCzQP4yy49Mdr08CSRH3iBtJwC42MJlF5CVAFlwMJ7C0NLwKYcuLXKu X-Received: by 10.60.42.162 with SMTP id p2mr46330958oel.27.1404169843055; Mon, 30 Jun 2014 16:10:43 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id cu7sm76370192oec.12.2014.06.30.16.10.41 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 16:10:42 -0700 (PDT) From: greg.bellows@linaro.org To: qemu-devel@nongnu.org Date: Mon, 30 Jun 2014 18:09:10 -0500 Message-Id: <1404169773-20264-11-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.172 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 10/33] target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler If EL3 is using Aarch64 IRQ/FIQ masking is ignored in all exception levels other than EL3 if SCR.{FIQ|IRQ} is set to 1 (routed to EL3). Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 98 +++++++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 72 insertions(+), 26 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index fbd7cad..7b2817c 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1211,20 +1211,43 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) * (table G1-18/G1-19) */ switch (excp_idx) { case EXCP_FIQ: + if (arm_feature(env, ARM_FEATURE_EL3) && arm_el_is_aa64(env, 3)) { + /* If EL3 is using Aarch64 and FIQs are routed to EL3 masking is + * ignored in all exception levels except EL3. + */ + if ((env->cp15.scr_el3 & SCR_FIQ) && cur_el < 3) { + return true; + } + /* If we are in EL3 but FIQs are not routed to EL3 the exception + * is not taken but remains pending. + */ + if (!(env->cp15.scr_el3 & SCR_FIQ) && cur_el == 3) { + return false; + } + } if (!secure) { - if (arm_feature(env, ARM_FEATURE_EL2) && - (env->cp15.hcr_el2 & HCR_FMO)) { - /* CPSR.F/PSTATE.F ignored if - * - exception is taken from Non-secure state - * - HCR.FMO == 1 - * - either: - not in Hyp mode - * - SCR.FIQ routes exception to monitor mode - */ - if (cur_el < 2) { - return true; - } else if (arm_feature(env, ARM_FEATURE_EL3) && - (env->cp15.scr_el3 & SCR_FIQ)) { - return true; + if (arm_feature(env, ARM_FEATURE_EL2)) { + if (env->cp15.hcr_el2 & HCR_FMO) { + /* CPSR.F/PSTATE.F ignored if + * - exception is taken from Non-secure state + * - HCR.FMO == 1 + * - either: - not in Hyp mode + * - SCR.FIQ routes exception to monitor mode + * (EL3 in Aarch32) + */ + if (cur_el < 2) { + return true; + } else if (arm_feature(env, ARM_FEATURE_EL3) && + (env->cp15.scr_el3 & SCR_FIQ) && + !arm_el_is_aa64(env, 3)) { + return true; + } + } else if (arm_el_is_aa64(env, 3) && + (env->cp15.scr_el3 & SCR_RW) && + cur_el == 2) { + /* FIQs not routed to EL2 but currently in EL2 (A64). + * Exception is not taken but remains pending. */ + return false; } } /* In ARMv7 only applies if both Security Extensions (EL3) and @@ -1252,20 +1275,43 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) } return !(env->daif & PSTATE_F); case EXCP_IRQ: + if (arm_feature(env, ARM_FEATURE_EL3) && arm_el_is_aa64(env, 3)) { + /* If EL3 is using Aarch64 and IRQs are routed to EL3 masking is + * ignored in all exception levels except EL3. + */ + if ((env->cp15.scr_el3 & SCR_IRQ) && cur_el < 3) { + return true; + } + /* If we are in EL3 but IRQ s are not routed to EL3 the exception + * is not taken but remains pending. + */ + if (!(env->cp15.scr_el3 & SCR_IRQ) && cur_el == 3) { + return false; + } + } if (!secure) { - if (arm_feature(env, ARM_FEATURE_EL2) && - (env->cp15.hcr_el2 & HCR_IMO)) { - /* CPSR.I/PSTATE.I ignored if - * - exception is taken from Non-secure state - * - HCR.IMO == 1 - * - either: - not in Hyp mode - * - SCR.IRQ routes exception to monitor mode - */ - if (cur_el < 2) { - return true; - } else if (arm_feature(env, ARM_FEATURE_EL3) && - (env->cp15.scr_el3 & SCR_IRQ)) { - return true; + if (arm_feature(env, ARM_FEATURE_EL2)) { + if (env->cp15.hcr_el2 & HCR_IMO) { + /* CPSR.I/PSTATE.I ignored if + * - exception is taken from Non-secure state + * - HCR.IMO == 1 + * - either: - not in Hyp mode + * - SCR.IRQ routes exception to monitor mode + * (EL3 in Aarch32) + */ + if (cur_el < 2) { + return true; + } else if (arm_feature(env, ARM_FEATURE_EL3) && + (env->cp15.scr_el3 & SCR_IRQ) && + !arm_el_is_aa64(env, 3)) { + return true; + } + } else if (arm_el_is_aa64(env, 3) && + (env->cp15.scr_el3 & SCR_RW) && + cur_el == 2) { + /* IRQs not routed to EL2 but currently in EL2 (A64). + * Exception is not taken but remains pending. */ + return false; } } }