From patchwork Thu May 29 14:15:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 353764 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7333C14007D for ; Fri, 30 May 2014 00:26:57 +1000 (EST) Received: from localhost ([::1]:48499 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wq1IE-0003ei-VF for incoming@patchwork.ozlabs.org; Thu, 29 May 2014 10:26:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42509) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wq1Hw-0003Hg-Rd for qemu-devel@nongnu.org; Thu, 29 May 2014 10:26:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wq1Hu-0001UX-3d for qemu-devel@nongnu.org; Thu, 29 May 2014 10:26:36 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:45598) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wq1Ht-0001U8-UP for qemu-devel@nongnu.org; Thu, 29 May 2014 10:26:34 -0400 Received: from [2001:470:d4ed:1:2db:dfff:fe14:52d] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1Wq1Hs-0007x2-4G; Thu, 29 May 2014 16:26:32 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.80) (envelope-from ) id 1Wq1Ho-0006wF-Cb; Thu, 29 May 2014 16:26:28 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Thu, 29 May 2014 16:15:04 +0200 Message-Id: <1401372904-23536-1-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:bc8:30d7:101::1 Cc: rth@twiddle.net, petar.jovanovic@imgtec.com, aurelien@aurel32.net, afaerber@suse.de Subject: [Qemu-devel] [PATCH] target-mips: copy CP0_Config1 into DisasContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In order to avoid access to the CPUMIPSState structure in the translator, keep a copy of CP0_Config1 into DisasContext. The whole register is read-only so it can be copied as a single value. Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 13cf29b..bb89413 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1066,6 +1066,7 @@ typedef struct DisasContext { uint32_t opcode; int singlestep_enabled; int insn_flags; + int32_t CP0_Config1; /* Routine used to access memory */ int mem_idx; uint32_t hflags, saved_hflags; @@ -1919,10 +1920,10 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, tcg_temp_free(t0); } -static void gen_cop1_ldst(CPUMIPSState *env, DisasContext *ctx, - uint32_t op, int rt, int rs, int16_t imm) +static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt, + int rs, int16_t imm) { - if (env->CP0_Config1 & (1 << CP0C1_FP)) { + if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); gen_flt_ldst(ctx, op, rt, rs, imm); } else { @@ -11789,7 +11790,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, } break; case POOL32F: - if (env->CP0_Config1 & (1 << CP0C1_FP)) { + if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { minor = ctx->opcode & 0x3f; check_cp1_enabled(ctx); switch (minor) { @@ -12303,7 +12304,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case SDC132: mips32_op = OPC_SDC1; do_cop1: - gen_cop1_ldst(env, ctx, mips32_op, rt, rs, imm); + gen_cop1_ldst(ctx, mips32_op, rt, rs, imm); break; case ADDIUPC: { @@ -14551,7 +14552,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx) case OPC_MOVCI: check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); - if (env->CP0_Config1 & (1 << CP0C1_FP)) { + if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, (ctx->opcode >> 16) & 1); @@ -15430,11 +15431,11 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx) case OPC_LDC1: case OPC_SWC1: case OPC_SDC1: - gen_cop1_ldst(env, ctx, op, rt, rs, imm); + gen_cop1_ldst(ctx, op, rt, rs, imm); break; case OPC_CP1: - if (env->CP0_Config1 & (1 << CP0C1_FP)) { + if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); op1 = MASK_CP1(ctx->opcode); switch (op1) { @@ -15496,7 +15497,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx) break; case OPC_CP3: - if (env->CP0_Config1 & (1 << CP0C1_FP)) { + if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); op1 = MASK_CP3(ctx->opcode); switch (op1) { @@ -15604,6 +15605,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, ctx.saved_pc = -1; ctx.singlestep_enabled = cs->singlestep_enabled; ctx.insn_flags = env->insn_flags; + ctx.CP0_Config1 = env->CP0_Config1; ctx.tb = tb; ctx.bstate = BS_NONE; /* Restore delay slot state from the tb context. */