From patchwork Wed May 28 07:35:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 353253 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C43A5140084 for ; Wed, 28 May 2014 17:40:40 +1000 (EST) Received: from localhost ([::1]:39952 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WpYTW-0004jY-El for incoming@patchwork.ozlabs.org; Wed, 28 May 2014 03:40:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56002) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WpYRf-0000kR-AW for qemu-devel@nongnu.org; Wed, 28 May 2014 03:38:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WpYRW-0006p9-WF for qemu-devel@nongnu.org; Wed, 28 May 2014 03:38:43 -0400 Received: from s16892447.onlinehome-server.info ([82.165.15.123]:43805) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WpYRW-0006p1-N9 for qemu-devel@nongnu.org; Wed, 28 May 2014 03:38:34 -0400 Received: from 4e56a431.skybroadband.com ([78.86.164.49] helo=kentang.lan) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1WpYRP-0007iN-Uu; Wed, 28 May 2014 08:38:34 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, blauwirbel@gmail.com, atar4qemu@gmail.com Date: Wed, 28 May 2014 08:35:42 +0100 Message-Id: <1401262543-17544-4-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1401262543-17544-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1401262543-17544-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 78.86.164.49 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 3/4] apb: handle reading/writing of IOMMU control registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org While the registers are documented as being 64-bit, Linux seems to access them in two halves as 2 x 32-bit accesses. Make sure that we can correctly handle this case. Signed-off-by: Mark Cave-Ayland --- hw/pci-host/apb.c | 103 +++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 100 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index e25791f..b57b034 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -46,6 +46,16 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) #define APB_DPRINTF(fmt, ...) #endif +/* debug IOMMU */ +//#define DEBUG_IOMMU + +#ifdef DEBUG_IOMMU +#define IOMMU_DPRINTF(fmt, ...) \ +do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) +#else +#define IOMMU_DPRINTF(fmt, ...) +#endif + /* * Chipset docs: * PBM: "UltraSPARC IIi User's Manual", @@ -70,8 +80,12 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) #define MAX_IVEC 0x40 #define NO_IRQ_REQUEST (MAX_IVEC + 1) +#define IOMMU_NREGS 3 +#define IOMMU_CTRL 0x0 +#define IOMMU_BASE 0x8 + typedef struct IOMMUState { - uint32_t regs[6]; + uint64_t regs[IOMMU_NREGS]; } IOMMUState; #define TYPE_APB "pbm" @@ -145,6 +159,89 @@ static inline void pbm_clear_request(APBState *s, unsigned int irq_num) s->irq_request = NO_IRQ_REQUEST; } +static void iommu_config_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + IOMMUState *is = opaque; + + IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx " val: %" PRIx64 + " size: %d\n", addr, val, size); + + switch (addr) { + case IOMMU_CTRL: + if (size == 4) { + is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL; + is->regs[IOMMU_CTRL >> 3] |= val << 32; + } else { + is->regs[IOMMU_CTRL] = val; + } + break; + case IOMMU_CTRL + 0x4: + is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL; + is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL; + break; + case IOMMU_BASE: + if (size == 4) { + is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL; + is->regs[IOMMU_BASE >> 3] |= val << 32; + } else { + is->regs[IOMMU_BASE] = val; + } + break; + case IOMMU_BASE + 0x4: + is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL; + is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL; + break; + default: + qemu_log_mask(LOG_UNIMP, + "apb iommu: Unimplemented register write " + "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", + addr, size, val); + break; + } +} + +static uint64_t iommu_config_read(void *opaque, hwaddr addr, unsigned size) +{ + IOMMUState *is = opaque; + uint64_t val; + + switch (addr) { + case IOMMU_CTRL: + if (size == 4) { + val = is->regs[IOMMU_CTRL >> 3] >> 32; + } else { + val = is->regs[IOMMU_CTRL >> 3]; + } + break; + case IOMMU_CTRL + 0x4: + val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL; + break; + case IOMMU_BASE: + if (size == 4) { + val = is->regs[IOMMU_BASE >> 3] >> 32; + } else { + val = is->regs[IOMMU_BASE >> 3]; + } + break; + case IOMMU_BASE + 0x4: + val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL; + break; + default: + qemu_log_mask(LOG_UNIMP, + "apb iommu: Unimplemented register read " + "reg 0x%" HWADDR_PRIx " size 0x%x\n", + addr, size); + val = 0; + break; + } + + IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx " val: %" PRIx64 + " size: %d\n", addr, val, size); + + return val; +} + static void apb_config_writel (void *opaque, hwaddr addr, uint64_t val, unsigned size) { @@ -158,7 +255,7 @@ static void apb_config_writel (void *opaque, hwaddr addr, /* XXX: not implemented yet */ break; case 0x200 ... 0x217: /* IOMMU */ - is->regs[(addr & 0xf) >> 2] = val; + iommu_config_write(is, (addr & 0xf), val, size); break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) { @@ -240,7 +337,7 @@ static uint64_t apb_config_readl (void *opaque, /* XXX: not implemented yet */ break; case 0x200 ... 0x217: /* IOMMU */ - val = is->regs[(addr & 0xf) >> 2]; + val = iommu_config_read(is, (addr & 0xf), size); break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) {