From patchwork Tue Mar 18 09:19:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvise Rigo X-Patchwork-Id: 331363 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 763B12C00CD for ; Tue, 18 Mar 2014 20:23:46 +1100 (EST) Received: from localhost ([::1]:34166 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPqFM-00047u-AR for incoming@patchwork.ozlabs.org; Tue, 18 Mar 2014 05:23:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34521) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPqBy-0005ke-Fn for qemu-devel@nongnu.org; Tue, 18 Mar 2014 05:20:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPqBr-0001g1-8S for qemu-devel@nongnu.org; Tue, 18 Mar 2014 05:20:14 -0400 Received: from mail-we0-f182.google.com ([74.125.82.182]:51448) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPqBr-0001ev-3F for qemu-devel@nongnu.org; Tue, 18 Mar 2014 05:20:07 -0400 Received: by mail-we0-f182.google.com with SMTP id p61so5680667wes.27 for ; Tue, 18 Mar 2014 02:20:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ck2mqEUQ1TR1mZQ2Xd8MjVtZ1iU2odpewctZbLKvlKs=; b=e0uiC/jrP5VmDt0LxAn6Nc+Esn8Psav7bvXCnG7DRLvclMUBnpqjE59Wn05Ktv+zd1 hdrugfI9yktvOyExOOGXd9F20IfW6h+Qeg+8MrEplP+mYXOPwY9JaEZz4dkhdgXyn4IM 7oMn2GE1AWWbvVOe0Ms96i93/CLiJpkMh9611knORWY7/bYZOt65paJ38NR+IyzcTp+X DE7KOGPlGuJU965lzo8e7bmwgI8/0EcoKlhHTMVSXqZXKkVmpAmiTlzG+5pgIHzjDYXn yzKLgVJR8Xo2s/IMnWLKDuQDNYUXlS45gy6VwTxTQvxvGzFx1gXm2TcdmZU0VT2GwJQM FaVA== X-Gm-Message-State: ALoCoQmMsT1oZQkPG/T65L6D09r+VtaSRU+ArPym+m9pI5HM+9YOqQCirc44rtJy3hlh7pnrKejI X-Received: by 10.181.13.11 with SMTP id eu11mr13502797wid.30.1395134406384; Tue, 18 Mar 2014 02:20:06 -0700 (PDT) Received: from localhost.localdomain (AGrenoble-651-1-406-154.w90-52.abo.wanadoo.fr. [90.52.42.154]) by mx.google.com with ESMTPSA id ee5sm32853410wib.8.2014.03.18.02.20.04 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 18 Mar 2014 02:20:05 -0700 (PDT) From: Alvise Rigo To: qemu-devel@nongnu.org Date: Tue, 18 Mar 2014 10:19:48 +0100 Message-Id: <1395134389-25778-7-git-send-email-a.rigo@virtualopensystems.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1395134389-25778-1-git-send-email-a.rigo@virtualopensystems.com> References: <1395134389-25778-1-git-send-email-a.rigo@virtualopensystems.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 74.125.82.182 Cc: Peter Maydell , tech@virtualopensystems.com, Alvise Rigo Subject: [Qemu-devel] [PATCH v2 6/7] target-arm: Added ADFSR/AIFSR and REVIDR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org These registers are required in TCG because they are migrated by KVM: their absence from the cpreg table leads to a migration failure. Signed-off-by: Alvise Rigo --- target-arm/cpu.h | 1 + target-arm/helper.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index adcfa42..2381fc5 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -170,6 +170,7 @@ typedef struct CPUARMState { /* System control coprocessor (cp15) */ struct { uint32_t c0_cpuid; + uint32_t c0_revid; uint64_t c0_cssel; /* Cache size selection. */ uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index daa707e..1fec33a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1456,6 +1456,10 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, }, + { .name = "ADFSR", .cp = 15, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, + .access = PL1_R, .resetvalue = 0, .type = ARM_CP_CONST, }, + { .name = "AIFSR", .cp = 15, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 1, + .access = PL1_R, .resetvalue = 0, .type = ARM_CP_CONST, }, { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1), @@ -2148,6 +2152,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), .type = ARM_CP_OVERRIDE }, + { .name = "REVIDR", + .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 6, + .access = PL1_R, .resetvalue = 0, + .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, + .fieldoffset = offsetof(CPUARMState, cp15.c0_revid),}, { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0, .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST },