From patchwork Fri Feb 21 06:44:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Yang Z" X-Patchwork-Id: 322441 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BD7352C0326 for ; Fri, 21 Feb 2014 17:50:01 +1100 (EST) Received: from localhost ([::1]:42385 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WGjvr-0002BF-Lx for incoming@patchwork.ozlabs.org; Fri, 21 Feb 2014 01:49:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53223) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WGjvE-0000ve-85 for qemu-devel@nongnu.org; Fri, 21 Feb 2014 01:49:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WGjv5-0007cs-Sh for qemu-devel@nongnu.org; Fri, 21 Feb 2014 01:49:20 -0500 Received: from mga02.intel.com ([134.134.136.20]:48867) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WGjv5-0007cJ-No for qemu-devel@nongnu.org; Fri, 21 Feb 2014 01:49:11 -0500 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 20 Feb 2014 22:49:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,517,1389772800"; d="scan'208";a="459295698" Received: from yang-desktopd.sh.intel.com (HELO yang-desktop.sh.intel.com) ([10.239.47.126]) by orsmga001.jf.intel.com with ESMTP; 20 Feb 2014 22:49:08 -0800 From: Yang Zhang To: qemu-devel@nongnu.org Date: Fri, 21 Feb 2014 14:44:11 +0800 Message-Id: <1392965053-1069-4-git-send-email-yang.z.zhang@intel.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1392965053-1069-1-git-send-email-yang.z.zhang@intel.com> References: <1392965053-1069-1-git-send-email-yang.z.zhang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Cc: peter.maydell@linaro.org, xen-devel@lists.xensource.com, stefano.stabellini@eu.citrix.com, allen.m.kay@intel.com, weidong.han@intel.com, jean.guyader@eu.citrix.com, Yang Zhang , anthony@codemonkey.ws, anthony.perard@citrix.com Subject: [Qemu-devel] [PATCH 3/5] xen, gfx passthrough: create intel isa bridge X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Yang Zhang ISA bridge is needed since Intel gfx drive will probe it instead of Dev31:Fun0 to make graphics device passthrough work easy for VMM, that only need to expose ISA bridge to let driver know the real hardware underneath. The original patch is from Allen Kay [allen.m.kay@intel.com] Signed-off-by: Yang Zhang Cc: Allen Kay --- hw/xen/xen_pt_graphics.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 71 insertions(+), 0 deletions(-) diff --git a/hw/xen/xen_pt_graphics.c b/hw/xen/xen_pt_graphics.c index 9ad8a74..54f16cf 100644 --- a/hw/xen/xen_pt_graphics.c +++ b/hw/xen/xen_pt_graphics.c @@ -162,3 +162,74 @@ out: free(bios); return rc; } + +static uint32_t isa_bridge_read_config(PCIDevice *d, uint32_t addr, int len) +{ + uint32_t v; + + v = pci_default_read_config(d, addr, len); + + return v; +} + +static void isa_bridge_write_config(PCIDevice *d, uint32_t addr, uint32_t v, + int len) +{ + pci_default_write_config(d, addr, v, len); + + return; +} + +static void isa_bridge_class_init(ObjectClass *klass, void *data) +{ + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->config_read = isa_bridge_read_config; + k->config_write = isa_bridge_write_config; + + return; +}; + +typedef struct { + PCIDevice dev; +} ISABridgeState; + +static TypeInfo isa_bridge_info = { + .name = "inte-pch-isa-bridge", + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(ISABridgeState), + .class_init = isa_bridge_class_init, +}; + +static void xen_pt_graphics_register_types(void) +{ + type_register_static(&isa_bridge_info); +} + +type_init(xen_pt_graphics_register_types) + +static int create_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) +{ + struct PCIDevice *dev; + + char rid; + + dev = pci_create(bus, PCI_DEVFN(0x1f, 0), "inte-pch-isa-bridge"); + if (!dev) { + XEN_PT_LOG(dev, "fail to create PCH ISA bridge.\n"); + return -1; + } + + qdev_init_nofail(&dev->qdev); + + pci_config_set_vendor_id(dev->config, hdev->vendor_id); + pci_config_set_device_id(dev->config, hdev->device_id); + + xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1); + + pci_config_set_revision(dev->config, rid); + pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_ISA); + + XEN_PT_LOG(dev, "Intel PCH ISA bridge is created.\n"); + return 0; +}