From patchwork Tue Feb 11 08:43:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 319173 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8CF542C00BA for ; Tue, 11 Feb 2014 19:46:50 +1100 (EST) Received: from localhost ([::1]:60261 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WD8zQ-0000fs-Gx for incoming@patchwork.ozlabs.org; Tue, 11 Feb 2014 03:46:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36378) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WD8xH-0006E4-GU for qemu-devel@nongnu.org; Tue, 11 Feb 2014 03:44:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WD8x9-0002go-2k for qemu-devel@nongnu.org; Tue, 11 Feb 2014 03:44:35 -0500 Received: from mail-lb0-x22f.google.com ([2a00:1450:4010:c04::22f]:63622) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WD8x8-0002gd-NS for qemu-devel@nongnu.org; Tue, 11 Feb 2014 03:44:27 -0500 Received: by mail-lb0-f175.google.com with SMTP id p9so5668977lbv.34 for ; Tue, 11 Feb 2014 00:44:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ueewCoNxx8Dre16IN+h1x/1rVu7r/P+ZyKcIkQWwLHA=; b=A/EBJnF23dNpk+TfAgR5AC7hoiXsqc01wi9hXpnR1392yIlrQLkQzMwOJXzQ3BcLp9 0X8bO70J8iQI85fuFB75BNNnLIocCfP4WkXKQzt/BINRprjHDF6ABHb/SwOpXUoeKPjQ AT8MKtx3lrsZFsqHxVNjLVePToYTf3U3/gdFRkeN8HePnkXxLPI5Hrw8aSf9C72h4lP/ 0ZO0fm/8Vp7rReeLJj80nj6H4xnyVYrXYL/APeODamQm4+V9gzZ5o+NUcEUczyu1rVgu esakTCS9GXnfZYd8eCOF09ICaPrTkYDz/N2YsGDUoFdrbdqxcIE/QyYr5HpNF5fgUag0 7pMA== X-Received: by 10.112.154.202 with SMTP id vq10mr24447652lbb.3.1392108265651; Tue, 11 Feb 2014 00:44:25 -0800 (PST) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPSA id k1sm18809833lbc.5.2014.02.11.00.44.24 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Feb 2014 00:44:24 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 11 Feb 2014 12:43:32 +0400 Message-Id: <1392108215-20794-4-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1392108215-20794-1-git-send-email-jcmvbkbc@gmail.com> References: <1392108215-20794-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:4010:c04::22f Cc: Max Filippov Subject: [Qemu-devel] [PATCH 3/6] target-xtensa: add basic checks to icache opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Check privilege level for privileged instructions (IHU, III, IIU and IPFL are privileged), memory accessibility for instructions that reference memory (IH* and IPFL) and windowed register validity for all instruction cache instructions. Signed-off-by: Max Filippov --- target-xtensa/helper.h | 1 + target-xtensa/op_helper.c | 5 +++++ target-xtensa/translate.c | 27 +++++++++++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/target-xtensa/helper.h b/target-xtensa/helper.h index 38d7157..322b04c 100644 --- a/target-xtensa/helper.h +++ b/target-xtensa/helper.h @@ -25,6 +25,7 @@ DEF_HELPER_2(advance_ccount, void, env, i32) DEF_HELPER_1(check_interrupts, void, env) DEF_HELPER_3(check_atomctl, void, env, i32, i32) +DEF_HELPER_2(itlb_hit_test, void, env, i32) DEF_HELPER_2(wsr_rasid, void, env, i32) DEF_HELPER_FLAGS_3(rtlb0, TCG_CALL_NO_RWG_SE, i32, env, i32, i32) DEF_HELPER_FLAGS_3(rtlb1, TCG_CALL_NO_RWG_SE, i32, env, i32, i32) diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index cf97025..c2dafd4 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -414,6 +414,11 @@ void HELPER(check_interrupts)(CPUXtensaState *env) check_interrupts(env); } +void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) +{ + get_page_addr_code(env, vaddr); +} + /*! * Check vaddr accessibility/cache attributes and raise an exception if * specified by the ATOMCTL SR. diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index f08bcfe..6061968 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -2336,22 +2336,42 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) #undef gen_dcache_hit_test4 #undef gen_dcache_hit_test8 +#define gen_icache_hit_test(w, shift) do { \ + TCGv_i32 addr = tcg_temp_new_i32(); \ + gen_window_check1(dc, RRI##w##_S); \ + tcg_gen_movi_i32(cpu_pc, dc->pc); \ + tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \ + RRI##w##_IMM##w << shift); \ + gen_helper_itlb_hit_test(cpu_env, addr); \ + tcg_temp_free(addr); \ + } while (0) + +#define gen_icache_hit_test4() gen_icache_hit_test(4, 4) +#define gen_icache_hit_test8() gen_icache_hit_test(8, 2) + case 12: /*IPFc*/ HAS_OPTION(XTENSA_OPTION_ICACHE); + gen_window_check1(dc, RRI8_S); break; case 13: /*ICEc*/ switch (OP1) { case 0: /*IPFLl*/ HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); + gen_check_privilege(dc); + gen_icache_hit_test4(); break; case 2: /*IHUl*/ HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); + gen_check_privilege(dc); + gen_icache_hit_test4(); break; case 3: /*IIUl*/ HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); + gen_check_privilege(dc); + gen_window_check1(dc, RRI4_S); break; default: /*reserved*/ @@ -2362,10 +2382,13 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) case 14: /*IHIc*/ HAS_OPTION(XTENSA_OPTION_ICACHE); + gen_icache_hit_test8(); break; case 15: /*IIIc*/ HAS_OPTION(XTENSA_OPTION_ICACHE); + gen_check_privilege(dc); + gen_window_check1(dc, RRI8_S); break; default: /*reserved*/ @@ -2374,6 +2397,10 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) } break; +#undef gen_icache_hit_test +#undef gen_icache_hit_test4 +#undef gen_icache_hit_test8 + case 9: /*L16SI*/ gen_load_store(ld16s, 1); break;