From patchwork Sun Dec 22 11:50:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 304465 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B96472C0078 for ; Sun, 22 Dec 2013 23:22:19 +1100 (EST) Received: from localhost ([::1]:57508 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vui2y-0008A9-JS for incoming@patchwork.ozlabs.org; Sun, 22 Dec 2013 07:22:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42525) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vui2N-0007xc-8F for qemu-devel@nongnu.org; Sun, 22 Dec 2013 07:21:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vui2H-0005Mz-MP for qemu-devel@nongnu.org; Sun, 22 Dec 2013 07:21:39 -0500 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:50539) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vui2H-0005Mn-Gj for qemu-devel@nongnu.org; Sun, 22 Dec 2013 07:21:33 -0500 Received: from [37.162.107.224] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1Vui2G-0004Ec-IO; Sun, 22 Dec 2013 13:21:32 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.80) (envelope-from ) id 1VuhYO-0002XM-2e; Sun, 22 Dec 2013 12:50:40 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sun, 22 Dec 2013 12:50:35 +0100 Message-Id: <1387713039-9584-6-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1387713039-9584-1-git-send-email-aurelien@aurel32.net> References: <1387713039-9584-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:bc8:30d7:101::1 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH v2 5/9] target-sh4: optimize negc using add2 and sub2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target-sh4/translate.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 21605b0..4ef0398 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -797,12 +797,12 @@ static void _decode_opc(DisasContext * ctx) return; case 0x600a: /* negc Rm,Rn */ { - TCGv t0 = tcg_temp_new(); - tcg_gen_neg_i32(t0, REG(B7_4)); - tcg_gen_sub_i32(REG(B11_8), t0, cpu_sr_t); - tcg_gen_setcondi_i32(TCG_COND_GTU, cpu_sr_t, t0, 0); - tcg_gen_setcond_i32(TCG_COND_GTU, t0, REG(B11_8), t0); - tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, t0); + TCGv t0 = tcg_const_i32(0); + tcg_gen_add2_i32(REG(B11_8), cpu_sr_t, + REG(B7_4), t0, cpu_sr_t, t0); + tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t, + t0, t0, REG(B11_8), cpu_sr_t); + tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1); tcg_temp_free(t0); } return;