From patchwork Sat Dec 21 16:58:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 304424 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 11D832C009C for ; Sun, 22 Dec 2013 04:00:19 +1100 (EST) Received: from localhost ([::1]:54818 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VuPuS-0006Xq-8s for incoming@patchwork.ozlabs.org; Sat, 21 Dec 2013 12:00:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53374) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VuPtf-0006NX-FV for qemu-devel@nongnu.org; Sat, 21 Dec 2013 11:59:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VuPtY-0002RF-Kp for qemu-devel@nongnu.org; Sat, 21 Dec 2013 11:59:27 -0500 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:46546) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VuPtY-0002QJ-7k for qemu-devel@nongnu.org; Sat, 21 Dec 2013 11:59:20 -0500 Received: from pc-97-206-86-200.cm.vtr.net ([200.86.206.97] helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1VuPtV-0005Hz-UN; Sat, 21 Dec 2013 17:59:18 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.80) (envelope-from ) id 1VuPtM-0003Tr-MI; Sat, 21 Dec 2013 17:59:08 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 21 Dec 2013 17:58:59 +0100 Message-Id: <1387645145-13069-3-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1387645145-13069-1-git-send-email-aurelien@aurel32.net> References: <1387645145-13069-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:bc8:30d7:101::1 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 2/8] target-sh4: Split out T from SR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In preparation for more efficient setting of this field. Signed-off-by: Aurelien Jarno --- target-sh4/cpu.h | 14 +++- target-sh4/gdbstub.c | 4 +- target-sh4/helper.c | 2 +- target-sh4/op_helper.c | 32 ++------ target-sh4/translate.c | 205 ++++++++++++++++++++---------------------------- 5 files changed, 110 insertions(+), 147 deletions(-) diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index c8ba70f..b7dd7ab 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -139,7 +139,8 @@ typedef struct CPUSH4State { uint32_t flags; /* general execution flags */ uint32_t gregs[24]; /* general registers */ float32 fregs[32]; /* floating point registers */ - uint32_t sr; /* status register */ + uint32_t sr; /* status register (with T split out) */ + uint32_t sr_t; /* T bit of status register */ uint32_t ssr; /* saved status register */ uint32_t spc; /* saved program counter */ uint32_t gbr; /* global base register */ @@ -339,6 +340,17 @@ static inline int cpu_ptel_pr (uint32_t ptel) #define TB_FLAG_PENDING_MOVCA (1 << 4) +static inline target_ulong cpu_read_sr(CPUSH4State *env) +{ + return (env->sr & ~(1u << SR_T)) | (env->sr_t << SR_T); +} + +static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr) +{ + env->sr_t = sr & (1u << SR_T); + env->sr = sr & ~(1u << SR_T); +} + static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, target_ulong *cs_base, int *flags) { diff --git a/target-sh4/gdbstub.c b/target-sh4/gdbstub.c index 05ba728..a365a27 100644 --- a/target-sh4/gdbstub.c +++ b/target-sh4/gdbstub.c @@ -51,7 +51,7 @@ int superh_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) case 21: return gdb_get_regl(mem_buf, env->macl); case 22: - return gdb_get_regl(mem_buf, env->sr); + return gdb_get_regl(mem_buf, cpu_read_sr(env)); case 23: return gdb_get_regl(mem_buf, env->fpul); case 24: @@ -111,7 +111,7 @@ int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->macl = ldl_p(mem_buf); break; case 22: - env->sr = ldl_p(mem_buf); + cpu_write_sr(env, ldl_p(mem_buf)); break; case 23: env->fpul = ldl_p(mem_buf); diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 07f8e91..a33db4d 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -162,7 +162,7 @@ void superh_cpu_do_interrupt(CPUState *cs) log_cpu_state(cs, 0); } - env->ssr = env->sr; + env->ssr = cpu_read_sr(env); env->spc = env->pc; env->sgr = env->gregs[15]; env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB); diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index 6d56df2..0e881a8 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -166,11 +166,11 @@ void helper_ocbi(CPUSH4State *env, uint32_t address) } } -#define T (env->sr & (1u << SR_T)) +#define T (env->sr_t) #define Q (env->sr & (1u << SR_Q) ? 1 : 0) #define M (env->sr & (1u << SR_M) ? 1 : 0) -#define SETT (env->sr |= (1u << SR_T)) -#define CLRT (env->sr &= ~(1u << SR_T)) +#define SETT (env->sr_t = 1) +#define CLRT (env->sr_t = 0) #define SETQ (env->sr |= (1u << SR_Q)) #define CLRQ (env->sr &= ~(1u << SR_Q)) #define SETM (env->sr |= (1u << SR_M)) @@ -319,16 +319,6 @@ void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1) } } -static inline void set_t(CPUSH4State *env) -{ - env->sr |= (1u << SR_T); -} - -static inline void clr_t(CPUSH4State *env) -{ - env->sr &= ~(1u << SR_T); -} - void helper_ld_fpscr(CPUSH4State *env, uint32_t val) { env->fpscr = val & FPSCR_MASK; @@ -413,10 +403,8 @@ void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1) relation = float32_compare(t0, t1, &env->fp_status); if (unlikely(relation == float_relation_unordered)) { update_fpscr(env, GETPC()); - } else if (relation == float_relation_equal) { - set_t(env); } else { - clr_t(env); + env->sr_t = (relation == float_relation_equal); } } @@ -428,10 +416,8 @@ void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1) relation = float64_compare(t0, t1, &env->fp_status); if (unlikely(relation == float_relation_unordered)) { update_fpscr(env, GETPC()); - } else if (relation == float_relation_equal) { - set_t(env); } else { - clr_t(env); + env->sr_t = (relation == float_relation_equal); } } @@ -443,10 +429,8 @@ void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1) relation = float32_compare(t0, t1, &env->fp_status); if (unlikely(relation == float_relation_unordered)) { update_fpscr(env, GETPC()); - } else if (relation == float_relation_greater) { - set_t(env); } else { - clr_t(env); + env->sr_t = (relation == float_relation_greater); } } @@ -458,10 +442,8 @@ void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1) relation = float64_compare(t0, t1, &env->fp_status); if (unlikely(relation == float_relation_unordered)) { update_fpscr(env, GETPC()); - } else if (relation == float_relation_greater) { - set_t(env); } else { - clr_t(env); + env->sr_t = (relation == float_relation_greater); } } diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 74425c3..d816936 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -59,7 +59,7 @@ enum { /* global register indexes */ static TCGv_ptr cpu_env; static TCGv cpu_gregs[24]; -static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr; +static TCGv cpu_pc, cpu_sr, cpu_sr_t, cpu_ssr, cpu_spc, cpu_gbr; static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_ldst; static TCGv cpu_fregs[32]; @@ -107,6 +107,8 @@ void sh4_translate_init(void) offsetof(CPUSH4State, pc), "PC"); cpu_sr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSH4State, sr), "SR"); + cpu_sr_t = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUSH4State, sr_t), "SR_T"); cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSH4State, ssr), "SSR"); cpu_spc = tcg_global_mem_new_i32(TCG_AREG0, @@ -153,7 +155,7 @@ void superh_cpu_dump_state(CPUState *cs, FILE *f, CPUSH4State *env = &cpu->env; int i; cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", - env->pc, env->sr, env->pr, env->fpscr); + env->pc, cpu_read_sr(env), env->pr, env->fpscr); cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n", env->spc, env->ssr, env->gbr, env->vbr); cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n", @@ -171,6 +173,17 @@ void superh_cpu_dump_state(CPUState *cs, FILE *f, env->delayed_pc); } } +static void gen_read_sr(TCGv dst) +{ + tcg_gen_andi_i32(dst, cpu_sr, ~(1u << SR_T)); + tcg_gen_or_i32(dst, dst, cpu_sr_t); +} + +static void gen_write_sr(TCGv src) +{ + tcg_gen_andi_i32(cpu_sr, src, ~(1u << SR_T)); + tcg_gen_andi_i32(cpu_sr_t, src, (1u << SR_T)); +} static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) { @@ -207,12 +220,9 @@ static void gen_jump(DisasContext * ctx) static inline void gen_branch_slot(uint32_t delayed_pc, int t) { - TCGv sr; int label = gen_new_label(); tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc); - sr = tcg_temp_new(); - tcg_gen_andi_i32(sr, cpu_sr, (1u << SR_T)); - tcg_gen_brcondi_i32(t ? TCG_COND_EQ:TCG_COND_NE, sr, 0, label); + tcg_gen_brcondi_i32(t ? TCG_COND_EQ : TCG_COND_NE, cpu_sr_t, 0, label); tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); gen_set_label(label); } @@ -221,13 +231,8 @@ static inline void gen_branch_slot(uint32_t delayed_pc, int t) static void gen_conditional_jump(DisasContext * ctx, target_ulong ift, target_ulong ifnott) { - int l1; - TCGv sr; - - l1 = gen_new_label(); - sr = tcg_temp_new(); - tcg_gen_andi_i32(sr, cpu_sr, (1u << SR_T)); - tcg_gen_brcondi_i32(TCG_COND_NE, sr, 0, l1); + int l1 = gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_sr_t, 0, l1); gen_goto_tb(ctx, 0, ifnott); gen_set_label(l1); gen_goto_tb(ctx, 1, ift); @@ -249,30 +254,6 @@ static void gen_delayed_conditional_jump(DisasContext * ctx) gen_jump(ctx); } -static inline void gen_cmp(int cond, TCGv t0, TCGv t1) -{ - TCGv t; - - t = tcg_temp_new(); - tcg_gen_setcond_i32(cond, t, t1, t0); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_T)); - tcg_gen_or_i32(cpu_sr, cpu_sr, t); - - tcg_temp_free(t); -} - -static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm) -{ - TCGv t; - - t = tcg_temp_new(); - tcg_gen_setcondi_i32(cond, t, t0, imm); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_T)); - tcg_gen_or_i32(cpu_sr, cpu_sr, t); - - tcg_temp_free(t); -} - static inline void gen_store_flags(uint32_t flags) { tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); @@ -408,8 +389,8 @@ static void _decode_opc(DisasContext * ctx) switch (ctx->opcode) { case 0x0019: /* div0u */ - tcg_gen_andi_i32(cpu_sr, cpu_sr, - ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T))); + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~((1u << SR_M) | (1u << SR_Q))); + tcg_gen_movi_i32(cpu_sr_t, 0); return; case 0x000b: /* rts */ CHECK_NOT_DELAY_SLOT @@ -425,7 +406,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_S)); return; case 0x0008: /* clrt */ - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_T)); + tcg_gen_movi_i32(cpu_sr_t, 0); return; case 0x0038: /* ldtlb */ CHECK_PRIVILEGED @@ -434,7 +415,7 @@ static void _decode_opc(DisasContext * ctx) case 0x002b: /* rte */ CHECK_PRIVILEGED CHECK_NOT_DELAY_SLOT - tcg_gen_mov_i32(cpu_sr, cpu_ssr); + gen_write_sr(cpu_ssr); tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); ctx->flags |= DELAY_SLOT; ctx->delayed_pc = (uint32_t) - 1; @@ -443,7 +424,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S)); return; case 0x0018: /* sett */ - tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_T)); + tcg_gen_movi_i32(cpu_sr_t, 1); return; case 0xfbfd: /* frchg */ tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR); @@ -658,22 +639,17 @@ static void _decode_opc(DisasContext * ctx) return; case 0x300e: /* addc Rm,Rn */ { - TCGv t0, t1, t2; + TCGv t0, t1; t0 = tcg_temp_new(); - tcg_gen_andi_i32(t0, cpu_sr, (1u << SR_T)); t1 = tcg_temp_new(); - tcg_gen_add_i32(t1, REG(B7_4), REG(B11_8)); - tcg_gen_add_i32(t0, t0, t1); - t2 = tcg_temp_new(); - tcg_gen_setcond_i32(TCG_COND_GTU, t2, REG(B11_8), t1); - tcg_gen_setcond_i32(TCG_COND_GTU, t1, t1, t0); - tcg_gen_or_i32(t1, t1, t2); - tcg_temp_free(t2); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_T)); - tcg_gen_or_i32(cpu_sr, cpu_sr, t1); - tcg_temp_free(t1); - tcg_gen_mov_i32(REG(B11_8), t0); + tcg_gen_add_i32(t0, REG(B7_4), REG(B11_8)); + tcg_gen_add_i32(t1, cpu_sr_t, t0); + tcg_gen_setcond_i32(TCG_COND_GTU, cpu_sr_t, REG(B11_8), t0); + tcg_gen_setcond_i32(TCG_COND_GTU, t0, t0, t1); + tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, t0); tcg_temp_free(t0); + tcg_gen_mov_i32(REG(B11_8), t1); + tcg_temp_free(t1); } return; case 0x300f: /* addv Rm,Rn */ @@ -685,11 +661,9 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_xor_i32(t1, t0, REG(B11_8)); t2 = tcg_temp_new(); tcg_gen_xor_i32(t2, REG(B7_4), REG(B11_8)); - tcg_gen_andc_i32(t1, t1, t2); + tcg_gen_andc_i32(cpu_sr_t, t1, t2); tcg_temp_free(t2); - tcg_gen_shri_i32(t1, t1, 31); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_T)); - tcg_gen_or_i32(cpu_sr, cpu_sr, t1); + tcg_gen_shri_i32(cpu_sr_t, cpu_sr_t, 31); tcg_temp_free(t1); tcg_gen_mov_i32(REG(B7_4), t0); tcg_temp_free(t0); @@ -699,38 +673,36 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4)); return; case 0x3000: /* cmp/eq Rm,Rn */ - gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8)); + tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), REG(B7_4)); return; case 0x3003: /* cmp/ge Rm,Rn */ - gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8)); + tcg_gen_setcond_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), REG(B7_4)); return; case 0x3007: /* cmp/gt Rm,Rn */ - gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8)); + tcg_gen_setcond_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), REG(B7_4)); return; case 0x3006: /* cmp/hi Rm,Rn */ - gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8)); + tcg_gen_setcond_i32(TCG_COND_GTU, cpu_sr_t, REG(B11_8), REG(B7_4)); return; case 0x3002: /* cmp/hs Rm,Rn */ - gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8)); + tcg_gen_setcond_i32(TCG_COND_GEU, cpu_sr_t, REG(B11_8), REG(B7_4)); return; case 0x200c: /* cmp/str Rm,Rn */ { TCGv cmp1 = tcg_temp_new(); TCGv cmp2 = tcg_temp_new(); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_T)); tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8)); tcg_gen_andi_i32(cmp2, cmp1, 0xff000000); - tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0); - tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, cmp2, 0); tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000); tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0); - tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2); + tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, cmp2); tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00); tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0); - tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2); + tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, cmp2); tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff); tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0); - tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2); + tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, cmp2); tcg_temp_free(cmp2); tcg_temp_free(cmp1); } @@ -740,8 +712,8 @@ static void _decode_opc(DisasContext * ctx) gen_copy_bit_i32(cpu_sr, SR_Q, REG(B11_8), 31); /* SR_Q */ gen_copy_bit_i32(cpu_sr, SR_M, REG(B7_4), 31); /* SR_M */ TCGv val = tcg_temp_new(); - tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8)); - gen_copy_bit_i32(cpu_sr, SR_T, val, 31); /* SR_T */ + tcg_gen_xor_i32(cpu_sr_t, REG(B7_4), REG(B11_8)); + tcg_gen_shri_i32(cpu_sr_t, cpu_sr_t, 31); /* SR_T */ tcg_temp_free(val); } return; @@ -826,19 +798,13 @@ static void _decode_opc(DisasContext * ctx) return; case 0x600a: /* negc Rm,Rn */ { - TCGv t0, t1; - t0 = tcg_temp_new(); + TCGv t0 = tcg_temp_new(); tcg_gen_neg_i32(t0, REG(B7_4)); - t1 = tcg_temp_new(); - tcg_gen_andi_i32(t1, cpu_sr, (1u << SR_T)); - tcg_gen_sub_i32(REG(B11_8), t0, t1); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_T)); - tcg_gen_setcondi_i32(TCG_COND_GTU, t1, t0, 0); - tcg_gen_or_i32(cpu_sr, cpu_sr, t1); - tcg_gen_setcond_i32(TCG_COND_GTU, t1, REG(B11_8), t0); - tcg_gen_or_i32(cpu_sr, cpu_sr, t1); + tcg_gen_sub_i32(REG(B11_8), t0, cpu_sr_t); + tcg_gen_setcondi_i32(TCG_COND_GTU, cpu_sr_t, t0, 0); + tcg_gen_setcond_i32(TCG_COND_GTU, t0, REG(B11_8), t0); + tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, t0); tcg_temp_free(t0); - tcg_temp_free(t1); } return; case 0x6007: /* not Rm,Rn */ @@ -919,17 +885,14 @@ static void _decode_opc(DisasContext * ctx) { TCGv t0, t1, t2; t0 = tcg_temp_new(); - tcg_gen_andi_i32(t0, cpu_sr, (1u << SR_T)); t1 = tcg_temp_new(); tcg_gen_sub_i32(t1, REG(B11_8), REG(B7_4)); - tcg_gen_sub_i32(t0, t1, t0); + tcg_gen_sub_i32(t0, t1, cpu_sr_t); t2 = tcg_temp_new(); tcg_gen_setcond_i32(TCG_COND_LTU, t2, REG(B11_8), t1); tcg_gen_setcond_i32(TCG_COND_LTU, t1, t1, t0); - tcg_gen_or_i32(t1, t1, t2); + tcg_gen_or_i32(cpu_sr_t, t1, t2); tcg_temp_free(t2); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_T)); - tcg_gen_or_i32(cpu_sr, cpu_sr, t1); tcg_temp_free(t1); tcg_gen_mov_i32(REG(B11_8), t0); tcg_temp_free(t0); @@ -946,9 +909,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_xor_i32(t2, REG(B11_8), REG(B7_4)); tcg_gen_and_i32(t1, t1, t2); tcg_temp_free(t2); - tcg_gen_shri_i32(t1, t1, 31); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_T)); - tcg_gen_or_i32(cpu_sr, cpu_sr, t1); + tcg_gen_shri_i32(cpu_sr_t, t1, 31); tcg_temp_free(t1); tcg_gen_mov_i32(REG(B11_8), t0); tcg_temp_free(t0); @@ -958,7 +919,7 @@ static void _decode_opc(DisasContext * ctx) { TCGv val = tcg_temp_new(); tcg_gen_and_i32(val, REG(B7_4), REG(B11_8)); - gen_cmp_imm(TCG_COND_EQ, val, 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); tcg_temp_free(val); } return; @@ -1197,7 +1158,7 @@ static void _decode_opc(DisasContext * ctx) ctx->flags |= DELAY_SLOT_CONDITIONAL; return; case 0x8800: /* cmp/eq #imm,R0 */ - gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(0), B7_0s); return; case 0xc400: /* mov.b @(disp,GBR),R0 */ { @@ -1313,7 +1274,7 @@ static void _decode_opc(DisasContext * ctx) { TCGv val = tcg_temp_new(); tcg_gen_andi_i32(val, REG(0), B7_0); - gen_cmp_imm(TCG_COND_EQ, val, 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); tcg_temp_free(val); } return; @@ -1323,7 +1284,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_add_i32(val, REG(0), cpu_gbr); tcg_gen_qemu_ld8u(val, val, ctx->memidx); tcg_gen_andi_i32(val, val, B7_0); - gen_cmp_imm(TCG_COND_EQ, val, 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); tcg_temp_free(val); } return; @@ -1386,14 +1347,14 @@ static void _decode_opc(DisasContext * ctx) ctx->delayed_pc = (uint32_t) - 1; return; case 0x4015: /* cmp/pl Rn */ - gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0); + tcg_gen_setcondi_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), 0); return; case 0x4011: /* cmp/pz Rn */ - gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0); + tcg_gen_setcondi_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), 0); return; case 0x4010: /* dt Rn */ tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); - gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), 0); return; case 0x402b: /* jmp @Rn */ CHECK_NOT_DELAY_SLOT @@ -1410,15 +1371,21 @@ static void _decode_opc(DisasContext * ctx) return; case 0x400e: /* ldc Rm,SR */ CHECK_PRIVILEGED - tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3); - ctx->bstate = BS_STOP; + { + TCGv val = tcg_temp_new(); + tcg_gen_andi_i32(val, REG(B11_8), 0x700083f3); + gen_write_sr(val); + tcg_temp_free(val); + ctx->bstate = BS_STOP; + } return; case 0x4007: /* ldc.l @Rm+,SR */ CHECK_PRIVILEGED { TCGv val = tcg_temp_new(); tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx); - tcg_gen_andi_i32(cpu_sr, val, 0x700083f3); + tcg_gen_andi_i32(val, val, 0x700083f3); + gen_write_sr(val); tcg_temp_free(val); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); ctx->bstate = BS_STOP; @@ -1426,15 +1393,18 @@ static void _decode_opc(DisasContext * ctx) return; case 0x0002: /* stc SR,Rn */ CHECK_PRIVILEGED - tcg_gen_mov_i32(REG(B11_8), cpu_sr); + gen_read_sr(REG(B11_8)); return; case 0x4003: /* stc SR,@-Rn */ CHECK_PRIVILEGED { TCGv addr = tcg_temp_new(); + TCGv val = tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); - tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx); + gen_read_sr(val); + tcg_gen_qemu_st32(val, addr, ctx->memidx); tcg_gen_mov_i32(REG(B11_8), addr); + tcg_temp_free(val); tcg_temp_free(addr); } return; @@ -1532,7 +1502,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); return; case 0x0029: /* movt Rn */ - tcg_gen_andi_i32(REG(B11_8), cpu_sr, (1u << SR_T)); + tcg_gen_mov_i32(REG(B11_8), cpu_sr_t); return; case 0x0073: /* MOVCO.L @@ -1542,8 +1512,7 @@ static void _decode_opc(DisasContext * ctx) */ if (ctx->features & SH_FEATURE_SH4A) { int label = gen_new_label(); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_T)); - tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst); + tcg_gen_mov_i32(cpu_sr, cpu_ldst); tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label); tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx); gen_set_label(label); @@ -1596,42 +1565,42 @@ static void _decode_opc(DisasContext * ctx) case 0x4024: /* rotcl Rn */ { TCGv tmp = tcg_temp_new(); - tcg_gen_mov_i32(tmp, cpu_sr); - gen_copy_bit_i32(cpu_sr, SR_T, REG(B11_8), 31); + tcg_gen_mov_i32(tmp, cpu_sr_t); + tcg_gen_shri_i32(cpu_sr_t, REG(B11_8), 31); tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); - gen_copy_bit_i32(REG(B11_8), SR_T, tmp, 0); + tcg_gen_or_i32(REG(B11_8), REG(B11_8), tmp); tcg_temp_free(tmp); } return; case 0x4025: /* rotcr Rn */ { TCGv tmp = tcg_temp_new(); - tcg_gen_mov_i32(tmp, cpu_sr); - gen_copy_bit_i32(cpu_sr, SR_T, REG(B11_8), 0); + tcg_gen_shli_i32(tmp, cpu_sr_t, 31); + tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 1); tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); - gen_copy_bit_i32(REG(B11_8), 31, tmp, 0); + tcg_gen_or_i32(REG(B11_8), REG(B11_8), tmp); tcg_temp_free(tmp); } return; case 0x4004: /* rotl Rn */ tcg_gen_rotli_i32(REG(B11_8), REG(B11_8), 1); - gen_copy_bit_i32(cpu_sr, SR_T, REG(B11_8), 0); + tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 0); return; case 0x4005: /* rotr Rn */ - gen_copy_bit_i32(cpu_sr, SR_T, REG(B11_8), 0); + tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 0); tcg_gen_rotri_i32(REG(B11_8), REG(B11_8), 1); return; case 0x4000: /* shll Rn */ case 0x4020: /* shal Rn */ - gen_copy_bit_i32(cpu_sr, SR_T, REG(B11_8), 31); + tcg_gen_shri_i32(cpu_sr_t, REG(B11_8), 31); tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); return; case 0x4021: /* shar Rn */ - gen_copy_bit_i32(cpu_sr, SR_T, REG(B11_8), 0); + tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 1); tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1); return; case 0x4001: /* shlr Rn */ - gen_copy_bit_i32(cpu_sr, SR_T, REG(B11_8), 0); + tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 1); tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); return; case 0x4008: /* shll2 Rn */ @@ -1659,7 +1628,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_mov_i32(addr, REG(B11_8)); val = tcg_temp_local_new(); tcg_gen_qemu_ld8u(val, addr, ctx->memidx); - gen_cmp_imm(TCG_COND_EQ, val, 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); tcg_gen_ori_i32(val, val, 0x80); tcg_gen_qemu_st8(val, addr, ctx->memidx); tcg_temp_free(val);