From patchwork Wed Dec 11 14:13:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 300222 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 30BEE2C0092 for ; Thu, 12 Dec 2013 03:25:12 +1100 (EST) Received: from localhost ([::1]:58302 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vqmaz-0003qM-Jc for incoming@patchwork.ozlabs.org; Wed, 11 Dec 2013 11:25:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53904) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqmYe-0008Sf-3p for qemu-devel@nongnu.org; Wed, 11 Dec 2013 11:22:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VqmYZ-0002LL-8C for qemu-devel@nongnu.org; Wed, 11 Dec 2013 11:22:44 -0500 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:47980) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqmYZ-0002LG-2Z for qemu-devel@nongnu.org; Wed, 11 Dec 2013 11:22:39 -0500 Received: from 185dhcp207.pl.eso.org ([134.171.185.207] helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1VqmYY-0005Oo-0Y; Wed, 11 Dec 2013 17:22:38 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.80) (envelope-from ) id 1VqkXH-0001yE-NU; Wed, 11 Dec 2013 15:13:11 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 11 Dec 2013 15:13:04 +0100 Message-Id: <1386771186-7442-3-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386771186-7442-1-git-send-email-aurelien@aurel32.net> References: <1386771186-7442-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:bc8:30d7:101::1 Cc: Paolo Bonzini , Aurelien Jarno Subject: [Qemu-devel] [PATCH v3 2/4] tcg/optimize: fix known-zero bits optimization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Known-zero bits optimization is a great idea that helps to generate more optimized code. However the current implementation only works in very few cases as the computed mask is not saved. Fix this to make it really working. Cc: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/optimize.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index c03d2f0..342c6e5 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -691,7 +691,8 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, break; } - /* Simplify using known-zero bits */ + /* Simplify using known-zero bits. Currently only ops with a single + output argument is supported. */ mask = -1; affected = -1; switch (op) { @@ -1153,6 +1154,11 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, } else { for (i = 0; i < def->nb_oargs; i++) { reset_temp(args[i]); + /* Save the corresponding known-zero bits mask for the + first output argument (only one supported so far). */ + if (i == 0) { + temps[args[i]].mask = mask; + } } } for (i = 0; i < def->nb_args; i++) {