From patchwork Wed Dec 11 14:13:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 300219 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B33F72C00A5 for ; Thu, 12 Dec 2013 03:22:36 +1100 (EST) Received: from localhost ([::1]:58271 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqmYT-0007bi-6w for incoming@patchwork.ozlabs.org; Wed, 11 Dec 2013 11:22:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53784) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqmY5-0007bY-4c for qemu-devel@nongnu.org; Wed, 11 Dec 2013 11:22:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VqmY0-0002BZ-NQ for qemu-devel@nongnu.org; Wed, 11 Dec 2013 11:22:09 -0500 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:47972) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqmY0-0002BN-HB for qemu-devel@nongnu.org; Wed, 11 Dec 2013 11:22:04 -0500 Received: from 185dhcp207.pl.eso.org ([134.171.185.207] helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1VqmXz-0005O4-8t; Wed, 11 Dec 2013 17:22:03 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.80) (envelope-from ) id 1VqkXH-0001yA-8O; Wed, 11 Dec 2013 15:13:11 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 11 Dec 2013 15:13:03 +0100 Message-Id: <1386771186-7442-2-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386771186-7442-1-git-send-email-aurelien@aurel32.net> References: <1386771186-7442-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:bc8:30d7:101::1 Cc: Paolo Bonzini , qemu-stable@nongnu.org, Aurelien Jarno Subject: [Qemu-devel] [PATCH v3 1/4] tcg/optimize: fix known-zero bits for right shift ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org 32-bit versions of sar and shr ops should not propagate known-zero bits from the unused 32 high bits. For sar it could even lead to wrong code being generated. Cc: Paolo Bonzini Cc: qemu-stable@nongnu.org Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/optimize.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 89e2d6a..c03d2f0 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -726,16 +726,29 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, mask = temps[args[1]].mask & mask; break; - CASE_OP_32_64(sar): + case INDEX_op_sar_i32: + if (temps[args[2]].state == TCG_TEMP_CONST) { + mask = ((int32_t)temps[args[1]].mask + >> temps[args[2]].val); + } + break; + case INDEX_op_sar_i64: if (temps[args[2]].state == TCG_TEMP_CONST) { - mask = ((tcg_target_long)temps[args[1]].mask + mask = ((int64_t)temps[args[1]].mask >> temps[args[2]].val); } break; - CASE_OP_32_64(shr): + case INDEX_op_shr_i32: if (temps[args[2]].state == TCG_TEMP_CONST) { - mask = temps[args[1]].mask >> temps[args[2]].val; + mask = ((uint32_t)temps[args[1]].mask + >> temps[args[2]].val); + } + break; + case INDEX_op_shr_i64: + if (temps[args[2]].state == TCG_TEMP_CONST) { + mask = ((uint64_t)temps[args[1]].mask + >> temps[args[2]].val); } break;