From patchwork Mon Sep 9 17:27:47 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 273623 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6FB182C00A6 for ; Tue, 10 Sep 2013 03:28:52 +1000 (EST) Received: from localhost ([::1]:52933 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJ5Gb-00053l-T8 for incoming@patchwork.ozlabs.org; Mon, 09 Sep 2013 13:28:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34676) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJ5G0-0004rn-1Z for qemu-devel@nongnu.org; Mon, 09 Sep 2013 13:28:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VJ5Fu-0008TN-BL for qemu-devel@nongnu.org; Mon, 09 Sep 2013 13:28:11 -0400 Received: from hall.aurel32.net ([2001:470:1f0b:4a8::1]:38647) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJ5Fu-0008T6-5E; Mon, 09 Sep 2013 13:28:06 -0400 Received: from anguille.univ-lyon1.fr ([134.214.4.207] helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1VJ5Fr-0003ka-Sz; Mon, 09 Sep 2013 19:28:03 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.80) (envelope-from ) id 1VJ5Fm-0006eL-3e; Mon, 09 Sep 2013 19:27:58 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 9 Sep 2013 19:27:47 +0200 Message-Id: <1378747670-25512-2-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1378747670-25512-1-git-send-email-aurelien@aurel32.net> References: <1378747670-25512-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:470:1f0b:4a8::1 Cc: Paolo Bonzini , qemu-stable@nongnu.org, Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH v2 1/4] tcg/optimize: fix known-zero bits for right shift ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org 32-bit versions of sar and shr ops should not propagate known-zero bits from the unused 32 high bits. For sar it could even lead to wrong code being generated. Cc: Richard Henderson Cc: Paolo Bonzini Cc: qemu-stable@nongnu.org Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- tcg/optimize.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index b29bf25..c539e39 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -730,16 +730,29 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, mask = temps[args[1]].mask & mask; break; - CASE_OP_32_64(sar): + case INDEX_op_sar_i32: + if (temps[args[2]].state == TCG_TEMP_CONST) { + mask = ((int32_t)temps[args[1]].mask + >> temps[args[2]].val); + } + break; + case INDEX_op_sar_i64: if (temps[args[2]].state == TCG_TEMP_CONST) { - mask = ((tcg_target_long)temps[args[1]].mask + mask = ((int64_t)temps[args[1]].mask >> temps[args[2]].val); } break; - CASE_OP_32_64(shr): + case INDEX_op_shr_i32: if (temps[args[2]].state == TCG_TEMP_CONST) { - mask = temps[args[1]].mask >> temps[args[2]].val; + mask = ((uint32_t)temps[args[1]].mask + >> temps[args[2]].val); + } + break; + case INDEX_op_shr_i64: + if (temps[args[2]].state == TCG_TEMP_CONST) { + mask = ((uint64_t)temps[args[1]].mask + >> temps[args[2]].val); } break;