From patchwork Tue Sep 3 06:27:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 272121 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 647922C00BF for ; Tue, 3 Sep 2013 16:28:59 +1000 (EST) Received: from localhost ([::1]:43513 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGk6j-0008Bf-8l for incoming@patchwork.ozlabs.org; Tue, 03 Sep 2013 02:28:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58887) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGk6F-0007w5-Os for qemu-devel@nongnu.org; Tue, 03 Sep 2013 02:28:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGk6A-0006kI-PY for qemu-devel@nongnu.org; Tue, 03 Sep 2013 02:28:27 -0400 Received: from hall.aurel32.net ([2001:470:1f0b:4a8::1]:34490) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGk6A-0006k5-IA for qemu-devel@nongnu.org; Tue, 03 Sep 2013 02:28:22 -0400 Received: from [37.161.145.56] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.2:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1VGk69-0001pM-IT; Tue, 03 Sep 2013 08:28:21 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1VGk5r-00039k-Qr; Tue, 03 Sep 2013 08:28:03 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2013 08:27:59 +0200 Message-Id: <1378189680-11987-4-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1378189680-11987-1-git-send-email-aurelien@aurel32.net> References: <1378189680-11987-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:470:1f0b:4a8::1 Cc: Paolo Bonzini , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH 3/4] tcg/optimize: improve known-zero bits for 32-bit ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The shl_i32 op might set some bits of the unused 32 high bits of the mask. Fix that by clearing the unused 32 high bits for all 32-bit ops except load/store which operate on tl values. Cc: Richard Henderson Cc: Paolo Bonzini Signed-off-by: Aurelien Jarno --- tcg/optimize.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index 0ed8983..b1f736b 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -791,6 +791,12 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, break; } + /* 32-bit ops (non 64-bit ops and non load/store ops) generate 32-bit + results */ + if (!(tcg_op_defs[op].flags & (TCG_OPF_CALL_CLOBBER | TCG_OPF_64BIT))) { + mask &= 0xffffffffu; + } + if (mask == 0) { assert(def->nb_oargs == 1); s->gen_opc_buf[op_index] = op_to_movi(op);