@@ -731,16 +731,29 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr,
mask = temps[args[1]].mask & mask;
break;
- CASE_OP_32_64(sar):
+ case INDEX_op_sar_i32:
+ if (temps[args[2]].state == TCG_TEMP_CONST) {
+ mask = ((int32_t)temps[args[1]].mask
+ >> temps[args[2]].val);
+ }
+ break;
+ case INDEX_op_sar_i64:
if (temps[args[2]].state == TCG_TEMP_CONST) {
- mask = ((tcg_target_long)temps[args[1]].mask
+ mask = ((int64_t)temps[args[1]].mask
>> temps[args[2]].val);
}
break;
- CASE_OP_32_64(shr):
+ case INDEX_op_shr_i32:
if (temps[args[2]].state == TCG_TEMP_CONST) {
- mask = temps[args[1]].mask >> temps[args[2]].val;
+ mask = ((uint32_t)temps[args[1]].mask
+ >> temps[args[2]].val);
+ }
+ break;
+ case INDEX_op_shr_i64:
+ if (temps[args[2]].state == TCG_TEMP_CONST) {
+ mask = ((uint64_t)temps[args[1]].mask
+ >> temps[args[2]].val);
}
break;
32-bit versions of sar and shr ops should not propagate known-zero bits from the unused 32 high bits. For sar it could even lead to wrong code being generated. Cc: Richard Henderson <rth@twiddle.net> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- tcg/optimize.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-)